Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2002 |
| 4 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Simon Glass | 6333448 | 2019-11-14 12:57:39 -0700 | [diff] [blame] | 8 | #include <cpu_func.h> |
Stefan Roese | eff3a0a | 2007-10-31 17:55:58 +0100 | [diff] [blame] | 9 | #include <asm/cache.h> |
Yuri Tikhonov | 18db5a6 | 2008-04-29 13:32:45 +0200 | [diff] [blame] | 10 | #include <watchdog.h> |
wdenk | 359733b | 2003-03-31 17:27:09 +0000 | [diff] [blame] | 11 | |
Rasmus Villemoes | dc32275 | 2021-04-21 11:16:03 +0200 | [diff] [blame] | 12 | static ulong maybe_watchdog_reset(ulong flushed) |
| 13 | { |
| 14 | flushed += CONFIG_SYS_CACHELINE_SIZE; |
| 15 | if (flushed >= CONFIG_CACHE_FLUSH_WATCHDOG_THRESHOLD) { |
| 16 | WATCHDOG_RESET(); |
| 17 | flushed = 0; |
| 18 | } |
| 19 | return flushed; |
| 20 | } |
| 21 | |
Dave Liu | 06ed90b | 2008-12-05 15:36:14 +0800 | [diff] [blame] | 22 | void flush_cache(ulong start_addr, ulong size) |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 23 | { |
Dave Liu | 06ed90b | 2008-12-05 15:36:14 +0800 | [diff] [blame] | 24 | ulong addr, start, end; |
Rasmus Villemoes | dc32275 | 2021-04-21 11:16:03 +0200 | [diff] [blame] | 25 | ulong flushed = 0; |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 26 | |
Dave Liu | 06ed90b | 2008-12-05 15:36:14 +0800 | [diff] [blame] | 27 | start = start_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1); |
| 28 | end = start_addr + size - 1; |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 29 | |
Kumar Gala | 3b967ae | 2009-02-06 08:08:06 -0600 | [diff] [blame] | 30 | for (addr = start; (addr <= end) && (addr >= start); |
| 31 | addr += CONFIG_SYS_CACHELINE_SIZE) { |
Dave Liu | 06ed90b | 2008-12-05 15:36:14 +0800 | [diff] [blame] | 32 | asm volatile("dcbst 0,%0" : : "r" (addr) : "memory"); |
Rasmus Villemoes | dc32275 | 2021-04-21 11:16:03 +0200 | [diff] [blame] | 33 | flushed = maybe_watchdog_reset(flushed); |
Dave Liu | 06ed90b | 2008-12-05 15:36:14 +0800 | [diff] [blame] | 34 | } |
| 35 | /* wait for all dcbst to complete on bus */ |
| 36 | asm volatile("sync" : : : "memory"); |
| 37 | |
Kumar Gala | 3b967ae | 2009-02-06 08:08:06 -0600 | [diff] [blame] | 38 | for (addr = start; (addr <= end) && (addr >= start); |
| 39 | addr += CONFIG_SYS_CACHELINE_SIZE) { |
Dave Liu | 06ed90b | 2008-12-05 15:36:14 +0800 | [diff] [blame] | 40 | asm volatile("icbi 0,%0" : : "r" (addr) : "memory"); |
Rasmus Villemoes | dc32275 | 2021-04-21 11:16:03 +0200 | [diff] [blame] | 41 | flushed = maybe_watchdog_reset(flushed); |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 42 | } |
Dave Liu | 06ed90b | 2008-12-05 15:36:14 +0800 | [diff] [blame] | 43 | asm volatile("sync" : : : "memory"); |
| 44 | /* flush prefetch queue */ |
| 45 | asm volatile("isync" : : : "memory"); |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 46 | } |