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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenkaffae2b2002-08-17 09:36:01 +00002/*
3 * (C) Copyright 2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
wdenkaffae2b2002-08-17 09:36:01 +00005 */
6
7#include <common.h>
Simon Glass63334482019-11-14 12:57:39 -07008#include <cpu_func.h>
Stefan Roeseeff3a0a2007-10-31 17:55:58 +01009#include <asm/cache.h>
Yuri Tikhonov18db5a62008-04-29 13:32:45 +020010#include <watchdog.h>
wdenk359733b2003-03-31 17:27:09 +000011
Rasmus Villemoesdc322752021-04-21 11:16:03 +020012static ulong maybe_watchdog_reset(ulong flushed)
13{
14 flushed += CONFIG_SYS_CACHELINE_SIZE;
15 if (flushed >= CONFIG_CACHE_FLUSH_WATCHDOG_THRESHOLD) {
16 WATCHDOG_RESET();
17 flushed = 0;
18 }
19 return flushed;
20}
21
Dave Liu06ed90b2008-12-05 15:36:14 +080022void flush_cache(ulong start_addr, ulong size)
wdenkaffae2b2002-08-17 09:36:01 +000023{
Dave Liu06ed90b2008-12-05 15:36:14 +080024 ulong addr, start, end;
Rasmus Villemoesdc322752021-04-21 11:16:03 +020025 ulong flushed = 0;
wdenkaffae2b2002-08-17 09:36:01 +000026
Dave Liu06ed90b2008-12-05 15:36:14 +080027 start = start_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
28 end = start_addr + size - 1;
wdenkaffae2b2002-08-17 09:36:01 +000029
Kumar Gala3b967ae2009-02-06 08:08:06 -060030 for (addr = start; (addr <= end) && (addr >= start);
31 addr += CONFIG_SYS_CACHELINE_SIZE) {
Dave Liu06ed90b2008-12-05 15:36:14 +080032 asm volatile("dcbst 0,%0" : : "r" (addr) : "memory");
Rasmus Villemoesdc322752021-04-21 11:16:03 +020033 flushed = maybe_watchdog_reset(flushed);
Dave Liu06ed90b2008-12-05 15:36:14 +080034 }
35 /* wait for all dcbst to complete on bus */
36 asm volatile("sync" : : : "memory");
37
Kumar Gala3b967ae2009-02-06 08:08:06 -060038 for (addr = start; (addr <= end) && (addr >= start);
39 addr += CONFIG_SYS_CACHELINE_SIZE) {
Dave Liu06ed90b2008-12-05 15:36:14 +080040 asm volatile("icbi 0,%0" : : "r" (addr) : "memory");
Rasmus Villemoesdc322752021-04-21 11:16:03 +020041 flushed = maybe_watchdog_reset(flushed);
wdenkaffae2b2002-08-17 09:36:01 +000042 }
Dave Liu06ed90b2008-12-05 15:36:14 +080043 asm volatile("sync" : : : "memory");
44 /* flush prefetch queue */
45 asm volatile("isync" : : : "memory");
wdenkaffae2b2002-08-17 09:36:01 +000046}