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wdenk3b759bd2002-03-31 16:14:24 +00001/*
2 * PowerPC memory management structures
3 */
4
5#ifndef _PPC_MMU_H_
6#define _PPC_MMU_H_
7
wdenk3b759bd2002-03-31 16:14:24 +00008#ifndef __ASSEMBLY__
9/* Hardware Page Table Entry */
Simon Glass4dcacfc2020-05-10 11:40:13 -060010#include <linux/bitops.h>
wdenk3b759bd2002-03-31 16:14:24 +000011typedef struct _PTE {
12#ifdef CONFIG_PPC64BRIDGE
13 unsigned long long vsid:52;
14 unsigned long api:5;
15 unsigned long :5;
16 unsigned long h:1;
17 unsigned long v:1;
18 unsigned long long rpn:52;
19#else /* CONFIG_PPC64BRIDGE */
20 unsigned long v:1; /* Entry is valid */
21 unsigned long vsid:24; /* Virtual segment identifier */
22 unsigned long h:1; /* Hash algorithm indicator */
23 unsigned long api:6; /* Abbreviated page index */
24 unsigned long rpn:20; /* Real (physical) page number */
25#endif /* CONFIG_PPC64BRIDGE */
26 unsigned long :3; /* Unused */
27 unsigned long r:1; /* Referenced */
28 unsigned long c:1; /* Changed */
29 unsigned long w:1; /* Write-thru cache mode */
30 unsigned long i:1; /* Cache inhibited */
31 unsigned long m:1; /* Memory coherence */
32 unsigned long g:1; /* Guarded */
33 unsigned long :1; /* Unused */
34 unsigned long pp:2; /* Page protection */
35} PTE;
36
37/* Values for PP (assumes Ks=0, Kp=1) */
38#define PP_RWXX 0 /* Supervisor read/write, User none */
39#define PP_RWRX 1 /* Supervisor read/write, User read */
40#define PP_RWRW 2 /* Supervisor read/write, User read/write */
41#define PP_RXRX 3 /* Supervisor read, User read */
42
43/* Segment Register */
44typedef struct _SEGREG {
45 unsigned long t:1; /* Normal or I/O type */
46 unsigned long ks:1; /* Supervisor 'key' (normally 0) */
47 unsigned long kp:1; /* User 'key' (normally 1) */
48 unsigned long n:1; /* No-execute */
49 unsigned long :4; /* Unused */
50 unsigned long vsid:24; /* Virtual Segment Identifier */
51} SEGREG;
52
53/* Block Address Translation (BAT) Registers */
54typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */
55 unsigned long bepi:15; /* Effective page index (virtual address) */
56 unsigned long :8; /* unused */
57 unsigned long w:1;
58 unsigned long i:1; /* Cache inhibit */
59 unsigned long m:1; /* Memory coherence */
60 unsigned long ks:1; /* Supervisor key (normally 0) */
61 unsigned long kp:1; /* User key (normally 1) */
62 unsigned long pp:2; /* Page access protections */
63} P601_BATU;
64
65typedef struct _BATU { /* Upper part of BAT (all except 601) */
66#ifdef CONFIG_PPC64BRIDGE
67 unsigned long long bepi:47;
68#else /* CONFIG_PPC64BRIDGE */
69 unsigned long bepi:15; /* Effective page index (virtual address) */
70#endif /* CONFIG_PPC64BRIDGE */
71 unsigned long :4; /* Unused */
72 unsigned long bl:11; /* Block size mask */
73 unsigned long vs:1; /* Supervisor valid */
74 unsigned long vp:1; /* User valid */
75} BATU;
76
77typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */
78 unsigned long brpn:15; /* Real page index (physical address) */
79 unsigned long :10; /* Unused */
80 unsigned long v:1; /* Valid bit */
81 unsigned long bl:6; /* Block size mask */
82} P601_BATL;
83
84typedef struct _BATL { /* Lower part of BAT (all except 601) */
85#ifdef CONFIG_PPC64BRIDGE
86 unsigned long long brpn:47;
87#else /* CONFIG_PPC64BRIDGE */
88 unsigned long brpn:15; /* Real page index (physical address) */
89#endif /* CONFIG_PPC64BRIDGE */
90 unsigned long :10; /* Unused */
91 unsigned long w:1; /* Write-thru cache */
92 unsigned long i:1; /* Cache inhibit */
93 unsigned long m:1; /* Memory coherence */
94 unsigned long g:1; /* Guarded (MBZ in IBAT) */
95 unsigned long :1; /* Unused */
96 unsigned long pp:2; /* Page access protections */
97} BATL;
98
99typedef struct _BAT {
100 BATU batu; /* Upper register */
101 BATL batl; /* Lower register */
102} BAT;
103
104typedef struct _P601_BAT {
105 P601_BATU batu; /* Upper register */
106 P601_BATL batl; /* Lower register */
107} P601_BAT;
108
109/*
110 * Simulated two-level MMU. This structure is used by the kernel
111 * to keep track of MMU mappings and is used to update/maintain
112 * the hardware HASH table which is really a cache of mappings.
113 *
114 * The simulated structures mimic the hardware available on other
115 * platforms, notably the 80x86 and 680x0.
116 */
117
118typedef struct _pte {
Jon Loeliger2267ba92006-10-13 16:47:53 -0500119 unsigned long page_num:20;
120 unsigned long flags:12; /* Page flags (some unused bits) */
wdenk3b759bd2002-03-31 16:14:24 +0000121} pte;
122
123#define PD_SHIFT (10+12) /* Page directory */
124#define PD_MASK 0x02FF
125#define PT_SHIFT (12) /* Page Table */
126#define PT_MASK 0x02FF
127#define PG_SHIFT (12) /* Page Entry */
128
129
130/* MMU context */
131
132typedef struct _MMU_context {
133 SEGREG segs[16]; /* Segment registers */
134 pte **pmap; /* Two-level page-map structure */
135} MMU_context;
136
137extern void _tlbie(unsigned long va); /* invalidate a TLB entry */
138extern void _tlbia(void); /* invalidate all TLB entries */
139
140typedef enum {
141 IBAT0 = 0, IBAT1, IBAT2, IBAT3,
Becky Bruce065b5772008-05-15 21:29:04 -0500142 DBAT0, DBAT1, DBAT2, DBAT3,
143#ifdef CONFIG_HIGH_BATS
144 IBAT4, IBAT5, IBAT6, IBAT7,
145 DBAT4, DBAT5, DBAT6, DBAT7
146#endif
wdenk3b759bd2002-03-31 16:14:24 +0000147} ppc_bat_t;
148
149extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower);
150extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
Becky Brucee7efd5b2008-05-09 15:41:35 -0500151extern void print_bats(void);
wdenk3b759bd2002-03-31 16:14:24 +0000152
153#endif /* __ASSEMBLY__ */
154
Becky Brucedad8c912009-02-03 18:10:51 -0600155#define BATU_VS 0x00000002
156#define BATU_VP 0x00000001
157#define BATU_INVALID 0x00000000
158
159#define BATL_WRITETHROUGH 0x00000040
160#define BATL_CACHEINHIBIT 0x00000020
161#define BATL_MEMCOHERENCE 0x00000010
162#define BATL_GUARDEDSTORAGE 0x00000008
163#define BATL_NO_ACCESS 0x00000000
164
165#define BATL_PP_MSK 0x00000003
166#define BATL_PP_00 0x00000000 /* No access */
167#define BATL_PP_01 0x00000001 /* Read-only */
168#define BATL_PP_10 0x00000002 /* Read-write */
169#define BATL_PP_11 0x00000003
170
171#define BATL_PP_NO_ACCESS BATL_PP_00
172#define BATL_PP_RO BATL_PP_01
173#define BATL_PP_RW BATL_PP_10
174
175/* BAT Block size values */
176#define BATU_BL_128K 0x00000000
177#define BATU_BL_256K 0x00000004
178#define BATU_BL_512K 0x0000000c
179#define BATU_BL_1M 0x0000001c
180#define BATU_BL_2M 0x0000003c
181#define BATU_BL_4M 0x0000007c
182#define BATU_BL_8M 0x000000fc
183#define BATU_BL_16M 0x000001fc
184#define BATU_BL_32M 0x000003fc
185#define BATU_BL_64M 0x000007fc
186#define BATU_BL_128M 0x00000ffc
187#define BATU_BL_256M 0x00001ffc
188
189/* Block lengths for processors that support extended block length */
190#ifdef HID0_XBSEN
191#define BATU_BL_512M 0x00003ffc
192#define BATU_BL_1G 0x00007ffc
193#define BATU_BL_2G 0x0000fffc
194#define BATU_BL_4G 0x0001fffc
195#define BATU_BL_MAX BATU_BL_4G
196#else
197#define BATU_BL_MAX BATU_BL_256M
198#endif
wdenk3b759bd2002-03-31 16:14:24 +0000199
200/* BAT Access Protection */
201#define BPP_XX 0x00 /* No access */
202#define BPP_RX 0x01 /* Read only */
203#define BPP_RW 0x02 /* Read/write */
204
Becky Brucef93e1cb2009-02-03 18:10:52 -0600205/* Macros to get values from BATs, once data is in the BAT register format */
206#define BATU_VALID(x) (x & 0x3)
207#define BATU_VADDR(x) (x & 0xfffe0000)
208#define BATL_PADDR(x) ((phys_addr_t)((x & 0xfffe0000) \
209 | ((x & 0x0e00ULL) << 24) \
210 | ((x & 0x04ULL) << 30)))
Timur Tabi107e9cd2010-03-29 12:51:07 -0500211#define BATU_SIZE(x) (1ULL << (fls((x & BATU_BL_MAX) >> 2) + 17))
212
213/* bytes into BATU_BL */
214#define TO_BATU_BL(x) \
215 (u32)((((1ull << __ilog2_u64((u64)x)) / (128 * 1024)) - 1) * 4)
Becky Brucef93e1cb2009-02-03 18:10:52 -0600216
wdenk3b759bd2002-03-31 16:14:24 +0000217/* Used to set up SDR1 register */
218#define HASH_TABLE_SIZE_64K 0x00010000
219#define HASH_TABLE_SIZE_128K 0x00020000
220#define HASH_TABLE_SIZE_256K 0x00040000
221#define HASH_TABLE_SIZE_512K 0x00080000
222#define HASH_TABLE_SIZE_1M 0x00100000
223#define HASH_TABLE_SIZE_2M 0x00200000
224#define HASH_TABLE_SIZE_4M 0x00400000
225#define HASH_TABLE_MASK_64K 0x000
226#define HASH_TABLE_MASK_128K 0x001
227#define HASH_TABLE_MASK_256K 0x003
228#define HASH_TABLE_MASK_512K 0x007
229#define HASH_TABLE_MASK_1M 0x00F
230#define HASH_TABLE_MASK_2M 0x01F
231#define HASH_TABLE_MASK_4M 0x03F
232
233/* Control/status registers for the MPC8xx.
234 * A write operation to these registers causes serialized access.
235 * During software tablewalk, the registers used perform mask/shift-add
236 * operations when written/read. A TLB entry is created when the Mx_RPN
237 * is written, and the contents of several registers are used to
238 * create the entry.
239 */
240#define MI_CTR 784 /* Instruction TLB control register */
241#define MI_GPM 0x80000000 /* Set domain manager mode */
242#define MI_PPM 0x40000000 /* Set subpage protection */
243#define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
244#define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */
245#define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
246#define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */
247#define MI_RESETVAL 0x00000000 /* Value of register at reset */
248
249/* These are the Ks and Kp from the PowerPC books. For proper operation,
250 * Ks = 0, Kp = 1.
251 */
252#define MI_AP 786
253#define MI_Ks 0x80000000 /* Should not be set */
254#define MI_Kp 0x40000000 /* Should always be set */
255
256/* The effective page number register. When read, contains the information
257 * about the last instruction TLB miss. When MI_RPN is written, bits in
258 * this register are used to create the TLB entry.
259 */
260#define MI_EPN 787
261#define MI_EPNMASK 0xfffff000 /* Effective page number for entry */
262#define MI_EVALID 0x00000200 /* Entry is valid */
263#define MI_ASIDMASK 0x0000000f /* ASID match value */
264 /* Reset value is undefined */
265
266/* A "level 1" or "segment" or whatever you want to call it register.
267 * For the instruction TLB, it contains bits that get loaded into the
268 * TLB entry when the MI_RPN is written.
269 */
270#define MI_TWC 789
271#define MI_APG 0x000001e0 /* Access protection group (0) */
272#define MI_GUARDED 0x00000010 /* Guarded storage */
273#define MI_PSMASK 0x0000000c /* Mask of page size bits */
274#define MI_PS8MEG 0x0000000c /* 8M page size */
275#define MI_PS512K 0x00000004 /* 512K page size */
276#define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */
277#define MI_SVALID 0x00000001 /* Segment entry is valid */
278 /* Reset value is undefined */
279
280/* Real page number. Defined by the pte. Writing this register
281 * causes a TLB entry to be created for the instruction TLB, using
282 * additional information from the MI_EPN, and MI_TWC registers.
283 */
284#define MI_RPN 790
285
286/* Define an RPN value for mapping kernel memory to large virtual
287 * pages for boot initialization. This has real page number of 0,
288 * large page size, shared page, cache enabled, and valid.
289 * Also mark all subpages valid and write access.
290 */
291#define MI_BOOTINIT 0x000001fd
292
293#define MD_CTR 792 /* Data TLB control register */
294#define MD_GPM 0x80000000 /* Set domain manager mode */
295#define MD_PPM 0x40000000 /* Set subpage protection */
296#define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
297#define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */
298#define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */
299#define MD_TWAM 0x04000000 /* Use 4K page hardware assist */
300#define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
301#define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */
302#define MD_RESETVAL 0x04000000 /* Value of register at reset */
303
304#define M_CASID 793 /* Address space ID (context) to match */
305#define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */
306
307
308/* These are the Ks and Kp from the PowerPC books. For proper operation,
309 * Ks = 0, Kp = 1.
310 */
311#define MD_AP 794
312#define MD_Ks 0x80000000 /* Should not be set */
313#define MD_Kp 0x40000000 /* Should always be set */
314
315/* The effective page number register. When read, contains the information
316 * about the last instruction TLB miss. When MD_RPN is written, bits in
317 * this register are used to create the TLB entry.
318 */
319#define MD_EPN 795
320#define MD_EPNMASK 0xfffff000 /* Effective page number for entry */
321#define MD_EVALID 0x00000200 /* Entry is valid */
322#define MD_ASIDMASK 0x0000000f /* ASID match value */
323 /* Reset value is undefined */
324
325/* The pointer to the base address of the first level page table.
326 * During a software tablewalk, reading this register provides the address
327 * of the entry associated with MD_EPN.
328 */
329#define M_TWB 796
330#define M_L1TB 0xfffff000 /* Level 1 table base address */
331#define M_L1INDX 0x00000ffc /* Level 1 index, when read */
332 /* Reset value is undefined */
333
334/* A "level 1" or "segment" or whatever you want to call it register.
335 * For the data TLB, it contains bits that get loaded into the TLB entry
336 * when the MD_RPN is written. It is also provides the hardware assist
337 * for finding the PTE address during software tablewalk.
338 */
339#define MD_TWC 797
340#define MD_L2TB 0xfffff000 /* Level 2 table base address */
341#define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */
342#define MD_APG 0x000001e0 /* Access protection group (0) */
343#define MD_GUARDED 0x00000010 /* Guarded storage */
344#define MD_PSMASK 0x0000000c /* Mask of page size bits */
345#define MD_PS8MEG 0x0000000c /* 8M page size */
346#define MD_PS512K 0x00000004 /* 512K page size */
347#define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */
348#define MD_WT 0x00000002 /* Use writethrough page attribute */
349#define MD_SVALID 0x00000001 /* Segment entry is valid */
350 /* Reset value is undefined */
351
352
353/* Real page number. Defined by the pte. Writing this register
354 * causes a TLB entry to be created for the data TLB, using
355 * additional information from the MD_EPN, and MD_TWC registers.
356 */
357#define MD_RPN 798
358
359/* This is a temporary storage register that could be used to save
360 * a processor working register during a tablewalk.
361 */
362#define M_TW 799
363
364/*
365 * At present, all PowerPC 400-class processors share a similar TLB
366 * architecture. The instruction and data sides share a unified,
367 * 64-entry, fully-associative TLB which is maintained totally under
368 * software control. In addition, the instruction side has a
369 * hardware-managed, 4-entry, fully- associative TLB which serves as a
370 * first level to the shared TLB. These two TLBs are known as the UTLB
371 * and ITLB, respectively.
372 */
373
374#define PPC4XX_TLB_SIZE 64
375
376/*
377 * TLB entries are defined by a "high" tag portion and a "low" data
378 * portion. On all architectures, the data portion is 32-bits.
379 *
380 * TLB entries are managed entirely under software control by reading,
381 * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
382 * instructions.
383 */
384
wdenk9c53f402003-10-15 23:53:47 +0000385/*
Kumar Gala4302ed72007-12-18 23:21:51 -0600386 * FSL Book-E support
wdenk9c53f402003-10-15 23:53:47 +0000387 */
388
Kumar Galad13eb3c2009-09-03 08:20:24 -0500389#define MAS0_TLBSEL_MSK 0x30000000
Timur Tabi918a35b2011-10-31 13:30:41 -0500390#define MAS0_TLBSEL(x) (((x) << 28) & MAS0_TLBSEL_MSK)
Kumar Galad13eb3c2009-09-03 08:20:24 -0500391#define MAS0_ESEL_MSK 0x0FFF0000
Timur Tabi918a35b2011-10-31 13:30:41 -0500392#define MAS0_ESEL(x) (((x) << 16) & MAS0_ESEL_MSK)
Kumar Gala4302ed72007-12-18 23:21:51 -0600393#define MAS0_NV(x) ((x) & 0x00000FFF)
wdenk9c53f402003-10-15 23:53:47 +0000394
Wolfgang Denka1be4762008-05-20 16:00:29 +0200395#define MAS1_VALID 0x80000000
Kumar Gala4302ed72007-12-18 23:21:51 -0600396#define MAS1_IPROT 0x40000000
Timur Tabi918a35b2011-10-31 13:30:41 -0500397#define MAS1_TID(x) (((x) << 16) & 0x3FFF0000)
Kumar Gala4302ed72007-12-18 23:21:51 -0600398#define MAS1_TS 0x00001000
Scott Wood33a619c2013-01-18 15:45:58 +0000399#define MAS1_TSIZE(x) (((x) << 7) & 0x00000F80)
400#define TSIZE_TO_BYTES(x) (1ULL << ((x) + 10))
wdenk9c53f402003-10-15 23:53:47 +0000401
Kumar Gala4302ed72007-12-18 23:21:51 -0600402#define MAS2_EPN 0xFFFFF000
403#define MAS2_X0 0x00000040
404#define MAS2_X1 0x00000020
405#define MAS2_W 0x00000010
406#define MAS2_I 0x00000008
407#define MAS2_M 0x00000004
408#define MAS2_G 0x00000002
409#define MAS2_E 0x00000001
wdenk9c53f402003-10-15 23:53:47 +0000410
Kumar Gala4302ed72007-12-18 23:21:51 -0600411#define MAS3_RPN 0xFFFFF000
412#define MAS3_U0 0x00000200
413#define MAS3_U1 0x00000100
414#define MAS3_U2 0x00000080
415#define MAS3_U3 0x00000040
416#define MAS3_UX 0x00000020
417#define MAS3_SX 0x00000010
418#define MAS3_UW 0x00000008
419#define MAS3_SW 0x00000004
420#define MAS3_UR 0x00000002
421#define MAS3_SR 0x00000001
wdenk9c53f402003-10-15 23:53:47 +0000422
Kumar Gala4302ed72007-12-18 23:21:51 -0600423#define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
424#define MAS4_TIDDSEL 0x000F0000
425#define MAS4_TSIZED(x) MAS1_TSIZE(x)
426#define MAS4_X0D 0x00000040
427#define MAS4_X1D 0x00000020
428#define MAS4_WD 0x00000010
429#define MAS4_ID 0x00000008
430#define MAS4_MD 0x00000004
431#define MAS4_GD 0x00000002
432#define MAS4_ED 0x00000001
wdenk9c53f402003-10-15 23:53:47 +0000433
Kumar Gala4302ed72007-12-18 23:21:51 -0600434#define MAS6_SPID0 0x3FFF0000
435#define MAS6_SPID1 0x00007FFE
436#define MAS6_SAS 0x00000001
437#define MAS6_SPID MAS6_SPID0
438
439#define MAS7_RPN 0xFFFFFFFF
wdenk9c53f402003-10-15 23:53:47 +0000440
Kumar Gala1ad4b3b2007-12-19 01:18:15 -0600441#define FSL_BOOKE_MAS0(tlbsel,esel,nv) \
442 (MAS0_TLBSEL(tlbsel) | MAS0_ESEL(esel) | MAS0_NV(nv))
443#define FSL_BOOKE_MAS1(v,iprot,tid,ts,tsize) \
444 ((((v) << 31) & MAS1_VALID) |\
445 (((iprot) << 30) & MAS1_IPROT) |\
446 (MAS1_TID(tid)) |\
447 (((ts) << 12) & MAS1_TS) |\
448 (MAS1_TSIZE(tsize)))
449#define FSL_BOOKE_MAS2(epn, wimge) \
450 (((epn) & MAS3_RPN) | (wimge))
451#define FSL_BOOKE_MAS3(rpn, user, perms) \
452 (((rpn) & MAS3_RPN) | (user) | (perms))
Kumar Galac417c912009-09-11 11:27:00 -0500453#define FSL_BOOKE_MAS7(rpn) \
454 (((u64)(rpn)) >> 32)
Kumar Gala1ad4b3b2007-12-19 01:18:15 -0600455
Scott Wood33a619c2013-01-18 15:45:58 +0000456#define BOOKE_PAGESZ_1K 0
457#define BOOKE_PAGESZ_2K 1
458#define BOOKE_PAGESZ_4K 2
459#define BOOKE_PAGESZ_8K 3
460#define BOOKE_PAGESZ_16K 4
461#define BOOKE_PAGESZ_32K 5
462#define BOOKE_PAGESZ_64K 6
463#define BOOKE_PAGESZ_128K 7
464#define BOOKE_PAGESZ_256K 8
465#define BOOKE_PAGESZ_512K 9
466#define BOOKE_PAGESZ_1M 10
467#define BOOKE_PAGESZ_2M 11
468#define BOOKE_PAGESZ_4M 12
469#define BOOKE_PAGESZ_8M 13
470#define BOOKE_PAGESZ_16M 14
471#define BOOKE_PAGESZ_32M 15
472#define BOOKE_PAGESZ_64M 16
473#define BOOKE_PAGESZ_128M 17
474#define BOOKE_PAGESZ_256M 18
475#define BOOKE_PAGESZ_512M 19
476#define BOOKE_PAGESZ_1G 20
477#define BOOKE_PAGESZ_2G 21
478#define BOOKE_PAGESZ_4G 22
479#define BOOKE_PAGESZ_8G 23
480#define BOOKE_PAGESZ_16GB 24
481#define BOOKE_PAGESZ_32GB 25
482#define BOOKE_PAGESZ_64GB 26
483#define BOOKE_PAGESZ_128GB 27
484#define BOOKE_PAGESZ_256GB 28
485#define BOOKE_PAGESZ_512GB 29
486#define BOOKE_PAGESZ_1TB 30
487#define BOOKE_PAGESZ_2TB 31
wdenk9c53f402003-10-15 23:53:47 +0000488
Scott Wood2bfa0f42012-08-20 13:10:08 +0000489#define TLBIVAX_ALL 4
490#define TLBIVAX_TLB0 0
491#define TLBIVAX_TLB1 8
492
Kumar Gala95bb67f2008-01-16 22:33:22 -0600493#ifdef CONFIG_E500
494#ifndef __ASSEMBLY__
495extern void set_tlb(u8 tlb, u32 epn, u64 rpn,
496 u8 perms, u8 wimge,
497 u8 ts, u8 esel, u8 tsize, u8 iprot);
498extern void disable_tlb(u8 esel);
499extern void invalidate_tlb(u8 tlb);
500extern void init_tlbs(void);
Kumar Galad13eb3c2009-09-03 08:20:24 -0500501extern int find_tlb_idx(void *addr, u8 tlbsel);
Kumar Gala42f99182009-11-12 10:26:16 -0600502extern void init_used_tlb_cams(void);
503extern int find_free_tlbcam(void);
Becky Bruce7b9cdb42010-06-17 11:37:22 -0500504extern void print_tlbcam(void);
Becky Brucef93e1cb2009-02-03 18:10:52 -0600505
Kumar Gala80f4bc72008-06-09 11:07:46 -0500506extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
Becky Bruce69694472011-07-18 18:49:15 -0500507extern void clear_ddr_tlbs(unsigned int memsize_in_meg);
Kumar Gala95bb67f2008-01-16 22:33:22 -0600508
Alexander Graf4c5d4262014-04-11 17:09:43 +0200509enum tlb_map_type {
510 TLB_MAP_RAM,
511 TLB_MAP_IO,
512};
513
514extern uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size,
515 enum tlb_map_type map_type);
516
Kumar Galac417c912009-09-11 11:27:00 -0500517extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7);
518
Kumar Gala95bb67f2008-01-16 22:33:22 -0600519#define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \
Kumar Galaf82885e2009-09-11 11:30:30 -0500520 { .mas0 = FSL_BOOKE_MAS0(_tlb, _esel, 0), \
521 .mas1 = FSL_BOOKE_MAS1(1, _iprot, 0, _ts, _sz), \
522 .mas2 = FSL_BOOKE_MAS2(_epn, _wimge), \
523 .mas3 = FSL_BOOKE_MAS3(_rpn, 0, _perms), \
524 .mas7 = FSL_BOOKE_MAS7(_rpn), }
Kumar Gala95bb67f2008-01-16 22:33:22 -0600525
526struct fsl_e_tlb_entry {
Kumar Galaf82885e2009-09-11 11:30:30 -0500527 u32 mas0;
528 u32 mas1;
529 u32 mas2;
530 u32 mas3;
531 u32 mas7;
Kumar Gala95bb67f2008-01-16 22:33:22 -0600532};
533
534extern struct fsl_e_tlb_entry tlb_table[];
535extern int num_tlb_entries;
536#endif
537#endif
538
Wolfgang Denk2f63bfe2009-09-25 00:57:49 +0200539#ifdef CONFIG_E300
Jon Loeliger5c8aa972006-04-26 17:58:56 -0500540#define LAWAR_EN 0x80000000
wdenk9c53f402003-10-15 23:53:47 +0000541#define LAWAR_SIZE 0x0000003F
542
543#define LAWAR_TRGT_IF_PCI 0x00000000
wdenk13eb2212004-07-09 23:27:13 +0000544#define LAWAR_TRGT_IF_PCI1 0x00000000
wdenk9c53f402003-10-15 23:53:47 +0000545#define LAWAR_TRGT_IF_PCIX 0x00000000
wdenk13eb2212004-07-09 23:27:13 +0000546#define LAWAR_TRGT_IF_PCI2 0x00100000
Kumar Gala1607da62007-11-29 02:18:59 -0600547#define LAWAR_TRGT_IF_PCIE1 0x00200000
548#define LAWAR_TRGT_IF_PCIE2 0x00100000
549#define LAWAR_TRGT_IF_PCIE3 0x00300000
wdenk9c53f402003-10-15 23:53:47 +0000550#define LAWAR_TRGT_IF_LBC 0x00400000
551#define LAWAR_TRGT_IF_CCSR 0x00800000
Jon Loeliger5c8aa972006-04-26 17:58:56 -0500552#define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000
wdenk9c53f402003-10-15 23:53:47 +0000553#define LAWAR_TRGT_IF_RIO 0x00c00000
554#define LAWAR_TRGT_IF_DDR 0x00f00000
Jon Loeliger8cf3c292006-08-22 17:54:05 -0500555#define LAWAR_TRGT_IF_DDR1 0x00f00000
556#define LAWAR_TRGT_IF_DDR2 0x01600000
wdenk9c53f402003-10-15 23:53:47 +0000557
558#define LAWAR_SIZE_BASE 0xa
559#define LAWAR_SIZE_4K (LAWAR_SIZE_BASE+1)
560#define LAWAR_SIZE_8K (LAWAR_SIZE_BASE+2)
561#define LAWAR_SIZE_16K (LAWAR_SIZE_BASE+3)
562#define LAWAR_SIZE_32K (LAWAR_SIZE_BASE+4)
563#define LAWAR_SIZE_64K (LAWAR_SIZE_BASE+5)
564#define LAWAR_SIZE_128K (LAWAR_SIZE_BASE+6)
565#define LAWAR_SIZE_256K (LAWAR_SIZE_BASE+7)
566#define LAWAR_SIZE_512K (LAWAR_SIZE_BASE+8)
567#define LAWAR_SIZE_1M (LAWAR_SIZE_BASE+9)
568#define LAWAR_SIZE_2M (LAWAR_SIZE_BASE+10)
569#define LAWAR_SIZE_4M (LAWAR_SIZE_BASE+11)
570#define LAWAR_SIZE_8M (LAWAR_SIZE_BASE+12)
571#define LAWAR_SIZE_16M (LAWAR_SIZE_BASE+13)
572#define LAWAR_SIZE_32M (LAWAR_SIZE_BASE+14)
573#define LAWAR_SIZE_64M (LAWAR_SIZE_BASE+15)
574#define LAWAR_SIZE_128M (LAWAR_SIZE_BASE+16)
575#define LAWAR_SIZE_256M (LAWAR_SIZE_BASE+17)
576#define LAWAR_SIZE_512M (LAWAR_SIZE_BASE+18)
577#define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19)
578#define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20)
Jon Loeliger8cf3c292006-08-22 17:54:05 -0500579#define LAWAR_SIZE_4G (LAWAR_SIZE_BASE+21)
580#define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22)
581#define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23)
582#define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24)
Kumar Gala9e36b822009-09-19 11:20:54 -0500583#endif
wdenk9c53f402003-10-15 23:53:47 +0000584
wdenk3b759bd2002-03-31 16:14:24 +0000585#endif /* _PPC_MMU_H_ */