Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2010-2011 Freescale Semiconductor, Inc. |
Biwen Li | 6a2d8d1 | 2020-05-01 20:04:13 +0800 | [diff] [blame] | 4 | * Copyright 2020 NXP |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | /* |
| 8 | * P010 RDB board configuration file |
| 9 | */ |
| 10 | |
| 11 | #ifndef __CONFIG_H |
| 12 | #define __CONFIG_H |
| 13 | |
Simon Glass | fb64e36 | 2020-05-10 11:40:09 -0600 | [diff] [blame] | 14 | #include <linux/stringify.h> |
| 15 | |
Prabhakar Kushwaha | d324f47 | 2013-04-16 13:27:44 +0530 | [diff] [blame] | 16 | #include <asm/config_mpc85xx.h> |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 17 | |
| 18 | #ifdef CONFIG_SDCARD |
Ying Zhang | 1233cbc | 2014-01-24 15:50:09 +0800 | [diff] [blame] | 19 | #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) |
| 20 | #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) |
| 21 | #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) |
| 22 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 23 | #endif |
| 24 | |
| 25 | #ifdef CONFIG_SPIFLASH |
Udit Agarwal | d2dd2f7 | 2019-11-07 16:11:39 +0000 | [diff] [blame] | 26 | #ifdef CONFIG_NXP_ESBC |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 27 | #define CONFIG_RAMBOOT_SPIFLASH |
Ruchika Gupta | 604a959 | 2014-09-29 11:14:35 +0530 | [diff] [blame] | 28 | #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc |
Ying Zhang | 1233cbc | 2014-01-24 15:50:09 +0800 | [diff] [blame] | 29 | #else |
Ying Zhang | 1233cbc | 2014-01-24 15:50:09 +0800 | [diff] [blame] | 30 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) |
| 31 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) |
| 32 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) |
| 33 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) |
Ying Zhang | 1233cbc | 2014-01-24 15:50:09 +0800 | [diff] [blame] | 34 | #endif |
| 35 | #endif |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 36 | |
Miquel Raynal | d093536 | 2019-10-03 19:50:03 +0200 | [diff] [blame] | 37 | #ifdef CONFIG_MTD_RAW_NAND |
Udit Agarwal | d2dd2f7 | 2019-11-07 16:11:39 +0000 | [diff] [blame] | 38 | #ifdef CONFIG_NXP_ESBC |
Prabhakar Kushwaha | f203656 | 2014-01-14 11:34:26 +0530 | [diff] [blame] | 39 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) |
Prabhakar Kushwaha | 66d6aa8 | 2013-04-16 13:28:12 +0530 | [diff] [blame] | 40 | #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) |
| 41 | #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 |
Ying Zhang | 1233cbc | 2014-01-24 15:50:09 +0800 | [diff] [blame] | 42 | #else |
Ying Zhang | 1233cbc | 2014-01-24 15:50:09 +0800 | [diff] [blame] | 43 | #ifdef CONFIG_TPL_BUILD |
Ying Zhang | 1233cbc | 2014-01-24 15:50:09 +0800 | [diff] [blame] | 44 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) |
| 45 | #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) |
| 46 | #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) |
Ying Zhang | 1233cbc | 2014-01-24 15:50:09 +0800 | [diff] [blame] | 47 | #elif defined(CONFIG_SPL_BUILD) |
Ying Zhang | 1233cbc | 2014-01-24 15:50:09 +0800 | [diff] [blame] | 48 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) |
| 49 | #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 |
| 50 | #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 |
Dipen Dudhat | 2f143ed | 2011-07-28 14:47:28 -0500 | [diff] [blame] | 51 | #endif |
Ying Zhang | 1233cbc | 2014-01-24 15:50:09 +0800 | [diff] [blame] | 52 | #endif |
| 53 | #endif |
Ruchika Gupta | b36ccc5 | 2011-06-08 22:52:48 -0500 | [diff] [blame] | 54 | |
| 55 | #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ |
Prabhakar Kushwaha | f203656 | 2014-01-14 11:34:26 +0530 | [diff] [blame] | 56 | #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc |
Ruchika Gupta | b36ccc5 | 2011-06-08 22:52:48 -0500 | [diff] [blame] | 57 | #endif |
| 58 | |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 59 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
| 60 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc |
| 61 | #endif |
| 62 | |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 63 | /* High Level Configuration Options */ |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 64 | |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 65 | #if defined(CONFIG_PCI) |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 66 | /* |
| 67 | * PCI Windows |
| 68 | * Memory space is mapped 1-1, but I/O space must start from 0. |
| 69 | */ |
| 70 | /* controller 1, Slot 1, tgtid 1, Base address a000 */ |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 71 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 |
| 72 | #ifdef CONFIG_PHYS_64BIT |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 73 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull |
| 74 | #else |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 75 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 |
| 76 | #endif |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 77 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 78 | #ifdef CONFIG_PHYS_64BIT |
| 79 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull |
| 80 | #else |
| 81 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 |
| 82 | #endif |
| 83 | |
| 84 | /* controller 2, Slot 2, tgtid 2, Base address 9000 */ |
Hou Zhiqiang | d3cb881 | 2020-05-01 19:06:28 +0800 | [diff] [blame] | 85 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 |
| 86 | #ifdef CONFIG_PHYS_64BIT |
| 87 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull |
| 88 | #else |
| 89 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 |
| 90 | #endif |
| 91 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 |
| 92 | #ifdef CONFIG_PHYS_64BIT |
| 93 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull |
| 94 | #else |
| 95 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 |
| 96 | #endif |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 97 | #endif |
| 98 | |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 99 | #define CONFIG_HWCONFIG |
| 100 | /* |
| 101 | * These can be toggled for performance analysis, otherwise use default. |
| 102 | */ |
| 103 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 104 | |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 105 | /* DDR Setup */ |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 106 | #define SPD_EEPROM_ADDRESS 0x52 |
| 107 | |
| 108 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
| 109 | |
| 110 | #ifndef __ASSEMBLY__ |
| 111 | extern unsigned long get_sdram_size(void); |
| 112 | #endif |
| 113 | #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ |
| 114 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
| 115 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
| 116 | |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 117 | /* DDR3 Controller Settings */ |
| 118 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f |
| 119 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 |
| 120 | #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 121 | #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 |
| 122 | #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 |
| 123 | #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 124 | #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 |
| 125 | #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 |
| 126 | #define CONFIG_SYS_DDR_RCW_1 0x00000000 |
| 127 | #define CONFIG_SYS_DDR_RCW_2 0x00000000 |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 128 | #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ |
| 129 | #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 130 | #define CONFIG_SYS_DDR_TIMING_4 0x00000001 |
| 131 | #define CONFIG_SYS_DDR_TIMING_5 0x03402400 |
| 132 | |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 133 | #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 |
| 134 | #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 |
| 135 | #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 136 | #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF |
| 137 | #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 138 | #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 |
| 139 | #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 140 | #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 141 | #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 142 | |
| 143 | /* settings for DDR3 at 667MT/s */ |
| 144 | #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 |
| 145 | #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 |
| 146 | #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 |
| 147 | #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD |
| 148 | #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 |
| 149 | #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 |
| 150 | #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 |
| 151 | #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 |
| 152 | #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 |
| 153 | |
| 154 | #define CONFIG_SYS_CCSRBAR 0xffe00000 |
| 155 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR |
| 156 | |
| 157 | /* |
| 158 | * Memory map |
| 159 | * |
| 160 | * 0x0000_0000 0x3fff_ffff DDR 1G cacheable |
| 161 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable |
| 162 | * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable |
| 163 | * |
| 164 | * Localbus non-cacheable |
| 165 | * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable |
| 166 | * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable |
| 167 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 |
| 168 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable |
| 169 | */ |
| 170 | |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 171 | /* |
| 172 | * IFC Definitions |
| 173 | */ |
| 174 | /* NOR Flash on IFC */ |
Prabhakar Kushwaha | 66d6aa8 | 2013-04-16 13:28:12 +0530 | [diff] [blame] | 175 | |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 176 | #define CONFIG_SYS_FLASH_BASE 0xee000000 |
| 177 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ |
| 178 | |
| 179 | #ifdef CONFIG_PHYS_64BIT |
| 180 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) |
| 181 | #else |
| 182 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
| 183 | #endif |
| 184 | |
| 185 | #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ |
| 186 | CSPR_PORT_SIZE_16 | \ |
| 187 | CSPR_MSEL_NOR | \ |
| 188 | CSPR_V) |
| 189 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) |
| 190 | #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) |
| 191 | /* NOR Flash Timing Params */ |
| 192 | #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ |
| 193 | FTIM0_NOR_TEADC(0x5) | \ |
| 194 | FTIM0_NOR_TEAHC(0x5) |
| 195 | #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ |
| 196 | FTIM1_NOR_TRAD_NOR(0x0f) |
| 197 | #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ |
| 198 | FTIM2_NOR_TCH(0x4) | \ |
| 199 | FTIM2_NOR_TWP(0x1c) |
| 200 | #define CONFIG_SYS_NOR_FTIM3 0x0 |
| 201 | |
| 202 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} |
| 203 | #define CONFIG_SYS_FLASH_QUIET_TEST |
| 204 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 205 | |
| 206 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 207 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 208 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
| 209 | |
| 210 | /* CFI for NOR Flash */ |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 211 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 212 | |
| 213 | /* NAND Flash on IFC */ |
| 214 | #define CONFIG_SYS_NAND_BASE 0xff800000 |
| 215 | #ifdef CONFIG_PHYS_64BIT |
| 216 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull |
| 217 | #else |
| 218 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
| 219 | #endif |
| 220 | |
Zhao Qiang | c655ef1 | 2013-09-26 09:10:32 +0800 | [diff] [blame] | 221 | #define CONFIG_MTD_PARTITION |
Zhao Qiang | c655ef1 | 2013-09-26 09:10:32 +0800 | [diff] [blame] | 222 | |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 223 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
| 224 | | CSPR_PORT_SIZE_8 \ |
| 225 | | CSPR_MSEL_NAND \ |
| 226 | | CSPR_V) |
| 227 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 228 | |
York Sun | 7f945ca | 2016-11-16 13:30:06 -0800 | [diff] [blame] | 229 | #if defined(CONFIG_TARGET_P1010RDB_PA) |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 230 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
| 231 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ |
| 232 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ |
| 233 | | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ |
| 234 | | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ |
| 235 | | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ |
| 236 | | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 237 | |
York Sun | 7f945ca | 2016-11-16 13:30:06 -0800 | [diff] [blame] | 238 | #elif defined(CONFIG_TARGET_P1010RDB_PB) |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 239 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
| 240 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ |
| 241 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ |
| 242 | | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ |
| 243 | | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ |
| 244 | | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ |
| 245 | | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 246 | #endif |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 247 | |
Dipen Dudhat | 2f143ed | 2011-07-28 14:47:28 -0500 | [diff] [blame] | 248 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
| 249 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
Dipen Dudhat | 2f143ed | 2011-07-28 14:47:28 -0500 | [diff] [blame] | 250 | |
York Sun | 7f945ca | 2016-11-16 13:30:06 -0800 | [diff] [blame] | 251 | #if defined(CONFIG_TARGET_P1010RDB_PA) |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 252 | /* NAND Flash Timing Params */ |
| 253 | #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ |
| 254 | FTIM0_NAND_TWP(0x0C) | \ |
| 255 | FTIM0_NAND_TWCHT(0x04) | \ |
| 256 | FTIM0_NAND_TWH(0x05) |
| 257 | #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ |
| 258 | FTIM1_NAND_TWBE(0x1d) | \ |
| 259 | FTIM1_NAND_TRR(0x07) | \ |
| 260 | FTIM1_NAND_TRP(0x0c) |
| 261 | #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ |
| 262 | FTIM2_NAND_TREH(0x05) | \ |
| 263 | FTIM2_NAND_TWHRE(0x0f) |
| 264 | #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) |
| 265 | |
York Sun | 7f945ca | 2016-11-16 13:30:06 -0800 | [diff] [blame] | 266 | #elif defined(CONFIG_TARGET_P1010RDB_PB) |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 267 | /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ |
| 268 | /* ONFI NAND Flash mode0 Timing Params */ |
| 269 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ |
| 270 | FTIM0_NAND_TWP(0x18) | \ |
| 271 | FTIM0_NAND_TWCHT(0x07) | \ |
| 272 | FTIM0_NAND_TWH(0x0a)) |
| 273 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ |
| 274 | FTIM1_NAND_TWBE(0x39) | \ |
| 275 | FTIM1_NAND_TRR(0x0e) | \ |
| 276 | FTIM1_NAND_TRP(0x18)) |
| 277 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ |
| 278 | FTIM2_NAND_TREH(0x0a) | \ |
| 279 | FTIM2_NAND_TWHRE(0x1e)) |
| 280 | #define CONFIG_SYS_NAND_FTIM3 0x0 |
| 281 | #endif |
| 282 | |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 283 | #define CONFIG_SYS_NAND_DDR_LAW 11 |
| 284 | |
| 285 | /* Set up IFC registers for boot location NOR/NAND */ |
Miquel Raynal | d093536 | 2019-10-03 19:50:03 +0200 | [diff] [blame] | 286 | #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT) |
Dipen Dudhat | 2f143ed | 2011-07-28 14:47:28 -0500 | [diff] [blame] | 287 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR |
| 288 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK |
| 289 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR |
| 290 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 |
| 291 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 |
| 292 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 |
| 293 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 |
| 294 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR |
| 295 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK |
| 296 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR |
| 297 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 |
| 298 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 |
| 299 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 |
| 300 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 |
| 301 | #else |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 302 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR |
| 303 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK |
| 304 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR |
| 305 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 |
| 306 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 |
| 307 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 |
| 308 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 |
| 309 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR |
| 310 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK |
| 311 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR |
| 312 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 |
| 313 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 |
| 314 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 |
| 315 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 |
Dipen Dudhat | 2f143ed | 2011-07-28 14:47:28 -0500 | [diff] [blame] | 316 | #endif |
| 317 | |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 318 | /* CPLD on IFC */ |
| 319 | #define CONFIG_SYS_CPLD_BASE 0xffb00000 |
| 320 | |
| 321 | #ifdef CONFIG_PHYS_64BIT |
| 322 | #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull |
| 323 | #else |
| 324 | #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE |
| 325 | #endif |
| 326 | |
| 327 | #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ |
| 328 | | CSPR_PORT_SIZE_8 \ |
| 329 | | CSPR_MSEL_GPCM \ |
| 330 | | CSPR_V) |
| 331 | #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) |
| 332 | #define CONFIG_SYS_CSOR3 0x0 |
| 333 | /* CPLD Timing parameters for IFC CS3 */ |
| 334 | #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ |
| 335 | FTIM0_GPCM_TEADC(0x0e) | \ |
| 336 | FTIM0_GPCM_TEAHC(0x0e)) |
| 337 | #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ |
| 338 | FTIM1_GPCM_TRAD(0x1f)) |
| 339 | #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ |
Shaohui Xie | c2bc460 | 2014-06-26 14:41:33 +0800 | [diff] [blame] | 340 | FTIM2_GPCM_TCH(0x8) | \ |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 341 | FTIM2_GPCM_TWP(0x1f)) |
| 342 | #define CONFIG_SYS_CS3_FTIM3 0x0 |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 343 | |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 344 | #define CONFIG_SYS_INIT_RAM_LOCK |
| 345 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ |
York Sun | 515fbb4 | 2016-04-06 13:22:10 -0700 | [diff] [blame] | 346 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 347 | |
Tom Rini | 55f3756 | 2022-05-24 14:14:02 -0400 | [diff] [blame] | 348 | #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 349 | |
Prabhakar Kushwaha | f402731 | 2014-03-31 15:31:48 +0530 | [diff] [blame] | 350 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 351 | |
Ying Zhang | 1233cbc | 2014-01-24 15:50:09 +0800 | [diff] [blame] | 352 | /* |
| 353 | * Config the L2 Cache as L2 SRAM |
| 354 | */ |
| 355 | #if defined(CONFIG_SPL_BUILD) |
| 356 | #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) |
| 357 | #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 |
| 358 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR |
| 359 | #define CONFIG_SYS_L2_SIZE (256 << 10) |
| 360 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) |
Miquel Raynal | d093536 | 2019-10-03 19:50:03 +0200 | [diff] [blame] | 361 | #elif defined(CONFIG_MTD_RAW_NAND) |
Ying Zhang | 1233cbc | 2014-01-24 15:50:09 +0800 | [diff] [blame] | 362 | #ifdef CONFIG_TPL_BUILD |
| 363 | #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 |
| 364 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR |
| 365 | #define CONFIG_SYS_L2_SIZE (256 << 10) |
| 366 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) |
Ying Zhang | 1233cbc | 2014-01-24 15:50:09 +0800 | [diff] [blame] | 367 | #else |
| 368 | #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 |
| 369 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR |
| 370 | #define CONFIG_SYS_L2_SIZE (256 << 10) |
| 371 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) |
Ying Zhang | 1233cbc | 2014-01-24 15:50:09 +0800 | [diff] [blame] | 372 | #endif |
| 373 | #endif |
| 374 | #endif |
| 375 | |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 376 | /* Serial Port */ |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 377 | #undef CONFIG_SERIAL_SOFTWARE_FIFO |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 378 | #define CONFIG_SYS_NS16550_SERIAL |
| 379 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 380 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
Tom Rini | 6b15c16 | 2022-05-13 12:26:35 -0400 | [diff] [blame] | 381 | #if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL) |
Dipen Dudhat | 2f143ed | 2011-07-28 14:47:28 -0500 | [diff] [blame] | 382 | #define CONFIG_NS16550_MIN_FUNCTIONS |
| 383 | #endif |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 384 | |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 385 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 386 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
| 387 | |
| 388 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| 389 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) |
| 390 | |
Heiko Schocher | f285074 | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 391 | /* I2C */ |
Shengzhou Liu | 36446ef | 2013-09-13 14:46:02 +0800 | [diff] [blame] | 392 | #define I2C_PCA9557_ADDR1 0x18 |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 393 | #define I2C_PCA9557_ADDR2 0x19 |
Shengzhou Liu | 36446ef | 2013-09-13 14:46:02 +0800 | [diff] [blame] | 394 | #define I2C_PCA9557_BUS_NUM 0 |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 395 | |
| 396 | /* I2C EEPROM */ |
York Sun | 7f945ca | 2016-11-16 13:30:06 -0800 | [diff] [blame] | 397 | #if defined(CONFIG_TARGET_P1010RDB_PB) |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 398 | #ifdef CONFIG_ID_EEPROM |
| 399 | #define CONFIG_SYS_I2C_EEPROM_NXID |
| 400 | #endif |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 401 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 |
| 402 | #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ |
| 403 | #endif |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 404 | /* enable read and write access to EEPROM */ |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 405 | |
| 406 | /* RTC */ |
| 407 | #define CONFIG_RTC_PT7C4338 |
| 408 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
| 409 | |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 410 | /* |
| 411 | * SPI interface will not be available in case of NAND boot SPI CS0 will be |
| 412 | * used for SLIC |
| 413 | */ |
Miquel Raynal | d093536 | 2019-10-03 19:50:03 +0200 | [diff] [blame] | 414 | #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT) |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 415 | /* eSPI - Enhanced SPI */ |
Dipen Dudhat | 2f143ed | 2011-07-28 14:47:28 -0500 | [diff] [blame] | 416 | #endif |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 417 | |
| 418 | #if defined(CONFIG_TSEC_ENET) |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 419 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ |
| 420 | #define CONFIG_TSEC1 1 |
| 421 | #define CONFIG_TSEC1_NAME "eTSEC1" |
| 422 | #define CONFIG_TSEC2 1 |
| 423 | #define CONFIG_TSEC2_NAME "eTSEC2" |
| 424 | #define CONFIG_TSEC3 1 |
| 425 | #define CONFIG_TSEC3_NAME "eTSEC3" |
| 426 | |
| 427 | #define TSEC1_PHY_ADDR 1 |
| 428 | #define TSEC2_PHY_ADDR 0 |
| 429 | #define TSEC3_PHY_ADDR 2 |
| 430 | |
| 431 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 432 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 433 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 434 | |
| 435 | #define TSEC1_PHYIDX 0 |
| 436 | #define TSEC2_PHYIDX 0 |
| 437 | #define TSEC3_PHYIDX 0 |
| 438 | |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 439 | /* TBI PHY configuration for SGMII mode */ |
| 440 | #define CONFIG_TSEC_TBICR_SETTINGS ( \ |
| 441 | TBICR_PHY_RESET \ |
| 442 | | TBICR_ANEG_ENABLE \ |
| 443 | | TBICR_FULL_DUPLEX \ |
| 444 | | TBICR_SPEED1_SET \ |
| 445 | ) |
| 446 | |
| 447 | #endif /* CONFIG_TSEC_ENET */ |
| 448 | |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 449 | #ifdef CONFIG_MMC |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 450 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
| 451 | #endif |
| 452 | |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 453 | /* |
| 454 | * Environment |
| 455 | */ |
Tom Rini | 5989fd4 | 2022-06-20 08:07:42 -0400 | [diff] [blame] | 456 | #if defined(CONFIG_MTD_RAW_NAND) |
Ying Zhang | 1233cbc | 2014-01-24 15:50:09 +0800 | [diff] [blame] | 457 | #ifdef CONFIG_TPL_BUILD |
Tom Rini | 5cd7ece | 2019-11-18 20:02:10 -0500 | [diff] [blame] | 458 | #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) |
Ying Zhang | 1233cbc | 2014-01-24 15:50:09 +0800 | [diff] [blame] | 459 | #endif |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 460 | #endif |
| 461 | |
| 462 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ |
| 463 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ |
| 464 | |
Tom Rini | ceed5d2 | 2017-05-12 22:33:27 -0400 | [diff] [blame] | 465 | #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \ |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 466 | || defined(CONFIG_FSL_SATA) |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 467 | #endif |
| 468 | |
| 469 | /* |
| 470 | * Miscellaneous configurable options |
| 471 | */ |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 472 | |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 473 | /* |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 474 | * For booting Linux, the board info and command line data |
| 475 | * have to be in the first 64 MB of memory, since this is |
| 476 | * the maximum mapped by the Linux kernel during initialization. |
| 477 | */ |
| 478 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 479 | |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 480 | /* |
| 481 | * Environment Configuration |
| 482 | */ |
| 483 | |
Joe Hershberger | 257ff78 | 2011-10-13 13:03:47 +0000 | [diff] [blame] | 484 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 485 | #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ |
| 486 | |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 487 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Marek Vasut | 0b3176c | 2012-09-23 17:41:24 +0200 | [diff] [blame] | 488 | "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 489 | "netdev=eth0\0" \ |
Marek Vasut | 0b3176c | 2012-09-23 17:41:24 +0200 | [diff] [blame] | 490 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 491 | "loadaddr=1000000\0" \ |
| 492 | "consoledev=ttyS0\0" \ |
| 493 | "ramdiskaddr=2000000\0" \ |
| 494 | "ramdiskfile=rootfs.ext2.gz.uboot\0" \ |
Scott Wood | b7f4b85 | 2016-07-19 17:52:06 -0500 | [diff] [blame] | 495 | "fdtaddr=1e00000\0" \ |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 496 | "fdtfile=p1010rdb.dtb\0" \ |
| 497 | "bdev=sda1\0" \ |
| 498 | "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ |
| 499 | "othbootargs=ramdisk_size=600000\0" \ |
| 500 | "usbfatboot=setenv bootargs root=/dev/ram rw " \ |
| 501 | "console=$consoledev,$baudrate $othbootargs; " \ |
| 502 | "usb start;" \ |
| 503 | "fatload usb 0:2 $loadaddr $bootfile;" \ |
| 504 | "fatload usb 0:2 $fdtaddr $fdtfile;" \ |
| 505 | "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ |
| 506 | "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ |
| 507 | "usbext2boot=setenv bootargs root=/dev/ram rw " \ |
| 508 | "console=$consoledev,$baudrate $othbootargs; " \ |
| 509 | "usb start;" \ |
| 510 | "ext2load usb 0:4 $loadaddr $bootfile;" \ |
| 511 | "ext2load usb 0:4 $fdtaddr $fdtfile;" \ |
| 512 | "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 513 | "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ |
Tom Rini | 8cd5d37 | 2022-02-25 11:19:49 -0500 | [diff] [blame] | 514 | BOOTMODE |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 515 | |
York Sun | 7f945ca | 2016-11-16 13:30:06 -0800 | [diff] [blame] | 516 | #if defined(CONFIG_TARGET_P1010RDB_PA) |
Tom Rini | 8cd5d37 | 2022-02-25 11:19:49 -0500 | [diff] [blame] | 517 | #define BOOTMODE \ |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 518 | "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ |
| 519 | "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ |
| 520 | "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ |
| 521 | "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ |
| 522 | "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ |
| 523 | "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" |
| 524 | |
York Sun | 7f945ca | 2016-11-16 13:30:06 -0800 | [diff] [blame] | 525 | #elif defined(CONFIG_TARGET_P1010RDB_PB) |
Tom Rini | 8cd5d37 | 2022-02-25 11:19:49 -0500 | [diff] [blame] | 526 | #define BOOTMODE \ |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 527 | "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ |
| 528 | "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ |
| 529 | "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ |
| 530 | "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ |
| 531 | "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ |
| 532 | "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ |
| 533 | "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ |
| 534 | "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ |
| 535 | "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ |
| 536 | "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" |
| 537 | #endif |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 538 | |
Ruchika Gupta | b36ccc5 | 2011-06-08 22:52:48 -0500 | [diff] [blame] | 539 | #include <asm/fsl_secure_boot.h> |
Ruchika Gupta | b36ccc5 | 2011-06-08 22:52:48 -0500 | [diff] [blame] | 540 | |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 541 | #endif /* __CONFIG_H */ |