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Yusuke Godacf236022008-03-11 12:55:12 +09001/*
2 * Configuation settings for the Renesas R7780MP board
3 *
Nobuhiro Iwamatsu3ac02122008-06-17 16:28:01 +09004 * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Yusuke Godacf236022008-03-11 12:55:12 +09005 * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Yusuke Godacf236022008-03-11 12:55:12 +09008 */
9
10#ifndef __R7780RP_H
11#define __R7780RP_H
12
13#undef DEBUG
Yusuke Godacf236022008-03-11 12:55:12 +090014#define CONFIG_SH4A 1
15#define CONFIG_CPU_SH7780 1
16#define CONFIG_R7780MP 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020017#define CONFIG_SYS_R7780MP_OLD_FLASH 1
Nobuhiro Iwamatsu3ac02122008-06-17 16:28:01 +090018#define __LITTLE_ENDIAN__ 1
Yusuke Godacf236022008-03-11 12:55:12 +090019
20/*
21 * Command line configuration.
22 */
23#define CONFIG_CMD_SDRAM
24#define CONFIG_CMD_FLASH
25#define CONFIG_CMD_MEMORY
26#define CONFIG_CMD_PCI
27#define CONFIG_CMD_NET
28#define CONFIG_CMD_PING
Mike Frysinger78dcaf42009-01-28 19:08:14 -050029#define CONFIG_CMD_SAVEENV
Yusuke Godacf236022008-03-11 12:55:12 +090030#define CONFIG_CMD_NFS
31#define CONFIG_CMD_IDE
32#define CONFIG_CMD_EXT2
33#define CONFIG_DOS_PARTITION
34
Jean-Christophe PLAGNIOL-VILLARD6ce9ea62008-08-13 01:40:38 +020035#define CONFIG_SCIF_CONSOLE 1
Yusuke Godacf236022008-03-11 12:55:12 +090036#define CONFIG_BAUDRATE 115200
37#define CONFIG_CONS_SCIF0 1
38
39#define CONFIG_BOOTDELAY 3
40#define CONFIG_BOOTARGS "console=ttySC0,115200"
41#define CONFIG_ENV_OVERWRITE 1
42
43/* check for keypress on bootdelay==0 */
44/*#define CONFIG_ZERO_BOOTDELAY_CHECK*/
45
Nobuhiro Iwamatsub816b982011-01-17 20:50:26 +090046#define CONFIG_SYS_TEXT_BASE 0x0FFC0000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020047#define CONFIG_SYS_SDRAM_BASE (0x08000000)
48#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
Yusuke Godacf236022008-03-11 12:55:12 +090049
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020050#define CONFIG_SYS_LONGHELP
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020051#define CONFIG_SYS_CBSIZE 256
52#define CONFIG_SYS_PBSIZE 256
53#define CONFIG_SYS_MAXARGS 16
54#define CONFIG_SYS_BARGSIZE 512
Yusuke Godacf236022008-03-11 12:55:12 +090055
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020056#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
Wolfgang Denk0708bc62010-10-07 21:51:12 +020057#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
Yusuke Godacf236022008-03-11 12:55:12 +090058
Nobuhiro Iwamatsu3ac02122008-06-17 16:28:01 +090059/* Flash board support */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020060#define CONFIG_SYS_FLASH_BASE (0xA0000000)
61#ifdef CONFIG_SYS_R7780MP_OLD_FLASH
Nobuhiro Iwamatsu3ac02122008-06-17 16:28:01 +090062/* NOR Flash (S29PL127J60TFI130) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020063# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
64# define CONFIG_SYS_MAX_FLASH_BANKS (2)
65# define CONFIG_SYS_MAX_FLASH_SECT 270
66# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
67 CONFIG_SYS_FLASH_BASE + 0x100000,\
68 CONFIG_SYS_FLASH_BASE + 0x400000,\
69 CONFIG_SYS_FLASH_BASE + 0x700000, }
70#else /* CONFIG_SYS_R7780MP_OLD_FLASH */
Nobuhiro Iwamatsu3ac02122008-06-17 16:28:01 +090071/* NOR Flash (Spantion S29GL256P) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020072# define CONFIG_SYS_MAX_FLASH_BANKS (1)
73# define CONFIG_SYS_MAX_FLASH_SECT 256
74# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
75#endif /* CONFIG_SYS_R7780MP_OLD_FLASH */
Yusuke Godacf236022008-03-11 12:55:12 +090076
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020077#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
Yusuke Godacf236022008-03-11 12:55:12 +090078/* Address of u-boot image in Flash */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020079#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
80#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
Yusuke Godacf236022008-03-11 12:55:12 +090081/* Size of DRAM reserved for malloc() use */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020082#define CONFIG_SYS_MALLOC_LEN (1204 * 1024)
Yusuke Godacf236022008-03-11 12:55:12 +090083
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020084#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
85#define CONFIG_SYS_RX_ETH_BUFFER (8)
Yusuke Godacf236022008-03-11 12:55:12 +090086
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020087#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +020088#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020089#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
90#undef CONFIG_SYS_FLASH_QUIET_TEST
Yusuke Godacf236022008-03-11 12:55:12 +090091/* print 'E' for empty sector on flinfo */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020092#define CONFIG_SYS_FLASH_EMPTY_INFO
Yusuke Godacf236022008-03-11 12:55:12 +090093
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +020094#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020095#define CONFIG_ENV_SECT_SIZE (256 * 1024)
96#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020097#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
98#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
99#define CONFIG_SYS_FLASH_WRITE_TOUT 500
Yusuke Godacf236022008-03-11 12:55:12 +0900100
101/* Board Clock */
102#define CONFIG_SYS_CLK_FREQ 33333333
Nobuhiro Iwamatsue6984492013-08-21 16:11:21 +0900103#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
104#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Jean-Christophe PLAGNIOL-VILLARD32e6acc2009-06-04 12:06:48 +0200105#define CONFIG_SYS_TMU_CLK_DIV 4
Yusuke Godacf236022008-03-11 12:55:12 +0900106
107/* PCI Controller */
108#if defined(CONFIG_CMD_PCI)
109#define CONFIG_PCI
110#define CONFIG_SH4_PCI
Nobuhiro Iwamatsu5aa5d672008-03-24 02:11:26 +0900111#define CONFIG_SH7780_PCI
Yoshihiro Shimoda30e055b2009-02-25 14:26:42 +0900112#define CONFIG_SH7780_PCI_LSR 0x07f00001
113#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE
114#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE
Yusuke Godacf236022008-03-11 12:55:12 +0900115#define CONFIG_PCI_PNP
116#define CONFIG_PCI_SCAN_SHOW 1
117#define __io
118#define __mem_pci
119
120#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
121#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
122#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
123
124#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
125#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
126#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
Nobuhiro Iwamatsu41773f52009-07-08 11:42:19 +0900127#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
128#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
129#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
Yusuke Godacf236022008-03-11 12:55:12 +0900130#endif /* CONFIG_CMD_PCI */
131
132#if defined(CONFIG_CMD_NET)
Nobuhiro Iwamatsu3ac02122008-06-17 16:28:01 +0900133/*
Nobuhiro Iwamatsu3ac02122008-06-17 16:28:01 +0900134#define CONFIG_RTL8169
135*/
Marcel Ziswilere7422af2009-09-09 21:09:00 +0200136/* AX88796L Support(NE2000 base chip) */
Yusuke Godacf236022008-03-11 12:55:12 +0900137#define CONFIG_DRIVER_AX88796L
138#define CONFIG_DRIVER_NE2000_BASE 0xA4100000
139#endif
140
141/* Compact flash Support */
142#if defined(CONFIG_CMD_IDE)
143#define CONFIG_IDE_RESET 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200144#define CONFIG_SYS_PIO_MODE 1
145#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
146#define CONFIG_SYS_IDE_MAXDEVICE 1
147#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
148#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
149#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
150#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
151#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
Albert Aribaud036c6b42010-08-08 05:17:05 +0530152#define CONFIG_IDE_SWAP_IO
Yusuke Godacf236022008-03-11 12:55:12 +0900153#endif /* CONFIG_CMD_IDE */
154
155#endif /* __R7780RP_H */