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Chander Kashyapbfef54d2011-05-24 20:02:56 +00001/*
2 * Lowlevel setup for SMDKV310 board based on S5PC210
3 *
4 * Copyright (C) 2011 Samsung Electronics
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <config.h>
26#include <version.h>
27#include <asm/arch/cpu.h>
28
29/*
30 * Register usages:
31 *
32 * r5 has zero always
33 * r7 has GPIO part1 base 0x11400000
34 * r6 has GPIO part2 base 0x11000000
35 */
36
37#define MEM_DLLl_ON
38
39_TEXT_BASE:
40 .word CONFIG_SYS_TEXT_BASE
41
42 .globl lowlevel_init
43lowlevel_init:
44 push {lr}
45
46 /* r5 has always zero */
47 mov r5, #0
48 ldr r7, =S5PC210_GPIO_PART1_BASE
49 ldr r6, =S5PC210_GPIO_PART2_BASE
50
51 /* check reset status */
52 ldr r0, =(S5PC210_POWER_BASE + 0x81C) @ INFORM7
53 ldr r1, [r0]
54
55 /* AFTR wakeup reset */
56 ldr r2, =S5P_CHECK_DIDLE
57 cmp r1, r2
58 beq exit_wakeup
59
60 /* Sleep wakeup reset */
61 ldr r2, =S5P_CHECK_SLEEP
62 cmp r1, r2
63 beq wakeup_reset
64
65 /*
66 * If U-boot is already running in ram, no need to relocate U-Boot.
67 * Memory controller must be configured before relocating U-Boot
68 * in ram.
69 */
70 ldr r0, =0x00ffffff /* r0 <- Mask Bits*/
71 bic r1, pc, r0 /* pc <- current addr of code */
72 /* r1 <- unmasked bits of pc */
73
74 ldr r2, _TEXT_BASE /* r2 <- original base addr in ram */
75 bic r2, r2, r0 /* r2 <- unmasked bits of r2*/
76 cmp r1, r2 /* compare r1, r2 */
77 beq 1f /* r0 == r1 then skip sdram init */
78
79 /* init system clock */
80 bl system_clock_init
81
82 /* Memory initialize */
83 bl mem_ctrl_asm_init
84
851:
86 /* for UART */
87 bl uart_asm_init
88 bl tzpc_init
89 pop {pc}
90
91wakeup_reset:
92 bl system_clock_init
93 bl mem_ctrl_asm_init
94 bl tzpc_init
95
96exit_wakeup:
97 /* Load return address and jump to kernel */
98 ldr r0, =(S5PC210_POWER_BASE + 0x800) @ INFORM0
99
100 /* r1 = physical address of s5pc210_cpu_resume function */
101 ldr r1, [r0]
102
103 /* Jump to kernel*/
104 mov pc, r1
105 nop
106 nop
107
108/*
109 * system_clock_init: Initialize core clock and bus clock.
110 * void system_clock_init(void)
111 */
112system_clock_init:
113 push {lr}
114 ldr r0, =S5PC210_CLOCK_BASE
115
116 /* APLL(1), MPLL(1), CORE(0), HPM(0) */
117 ldr r1, =0x0101
118 ldr r2, =0x14200 @CLK_SRC_CPU
119 str r1, [r0, r2]
120
121 /* wait ?us */
122 mov r1, #0x10000
1232: subs r1, r1, #1
124 bne 2b
125
126 ldr r1, =0x00
127 ldr r2, =0x0C210 @CLK_SRC_TOP0
128 str r1, [r0, r2]
129
130 ldr r1, =0x00
131 ldr r2, =0x0C214 @CLK_SRC_TOP1_OFFSET
132 str r1, [r0, r2]
133
134 /* DMC */
135 ldr r1, =0x00
136 ldr r2, =0x10200 @CLK_SRC_DMC_OFFSET
137 str r1, [r0, r2]
138
139 /*CLK_SRC_LEFTBUS */
140 ldr r1, =0x00
141 ldr r2, =0x04200 @CLK_SRC_LEFTBUS_OFFSET
142 str r1, [r0, r2]
143
144 /*CLK_SRC_RIGHTBUS */
145 ldr r1, =0x00
146 ldr r2, =0x08200 @CLK_SRC_RIGHTBUS_OFFSET
147 str r1, [r0, r2]
148
149 /* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
150 ldr r1, =0x066666
151 ldr r2, =0x0C240 @ CLK_SRC_FSYS
152 str r1, [r0, r2]
153
154 /* UART[0:4], PWM: SCLKMPLL(6) */
155 ldr r1, =0x06666666
156 ldr r2, =0x0C250 @CLK_SRC_PERIL0_OFFSET
157 str r1, [r0, r2]
158
159 /* wait ?us */
160 mov r1, #0x10000
1613: subs r1, r1, #1
162 bne 3b
163
164 /*
165 * CLK_DIV_CPU0:
166 *
167 * PCLK_DBG_RATIO[20] 0x1
168 * ATB_RATIO[16] 0x3
169 * PERIPH_RATIO[12] 0x3
170 * COREM1_RATIO[8] 0x7
171 * COREM0_RATIO[4] 0x3
172 */
Chander Kashyapbeeda8c2011-05-26 01:10:34 +0000173 ldr r1, =0x0133730
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000174 ldr r2, =0x14500 @CLK_DIV_CPU0_OFFSET
175 str r1, [r0, r2]
176
177 /* CLK_DIV_CPU1: COPY_RATIO [0] 0x3 */
178 ldr r1, =0x03
179 ldr r2, =0x14504 @CLK_DIV_CPU1_OFFSET
180 str r1, [r0, r2]
181
182 /*
183 * CLK_DIV_DMC0:
184 *
185 * CORE_TIMERS_RATIO[28] 0x1
186 * COPY2_RATIO[24] 0x3
187 * DMCP_RATIO[20] 0x1
188 * DMCD_RATIO[16] 0x1
189 * DMC_RATIO[12] 0x1
190 * DPHY_RATIO[8] 0x1
191 * ACP_PCLK_RATIO[4] 0x1
192 * ACP_RATIO[0] 0x3
193 */
194 ldr r1, =0x13111113
195 ldr r2, =0x010500 @CLK_DIV_DMC0_OFFSET
196 str r1, [r0, r2]
197
198 /*
199 * CLK_DIV_DMC1:
200 *
201 * DPM_RATIO[24] 0x1
202 * DVSEM_RATIO[16] 0x1
203 * PWI_RATIO[8] 0x1
204 */
205 ldr r1, =0x01010100
206 ldr r2, =0x010504 @CLK_DIV_DMC1_OFFSET
207 str r1, [r0, r2]
208
209 /*
210 * CLK_DIV_LEFRBUS:
211 *
212 * GPL_RATIO[4] 0x1
213 * GDL_RATIO[0] 0x3
214 */
215 ldr r1, =0x013
216 ldr r2, =0x04500 @CLK_DIV_LEFTBUS_OFFSET
217 str r1, [r0, r2]
218
219 /*
220 * CLK_DIV_RIGHTBUS:
221 *
222 * GPR_RATIO[4] 0x1
223 * GDR_RATIO[0] 0x3
224 */
225 ldr r1, =0x013
226 ldr r2, =0x08500 @CLK_DIV_RIGHTBUS_OFFSET
227 str r1, [r0, r2]
228
229 /*
230 * CLK_DIV_TOP:
231 *
232 * ONENAND_RATIO[16] 0x0
233 * ACLK_133_RATIO[12] 0x5
234 * ACLK_160_RATIO[8] 0x4
235 * ACLK_100_RATIO[4] 0x7
236 * ACLK_200_RATIO[0] 0x3
237 */
238 ldr r1, =0x05473
239 ldr r2, =0x0C510 @CLK_DIV_TOP_OFFSET
240 str r1, [r0, r2]
241
242 /* MMC[0:1] */
243 ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */
244 ldr r2, =0x0C544 @ CLK_DIV_FSYS1
245 str r1, [r0, r2]
246
247 /* MMC[2:3] */
Chander Kashyapbeeda8c2011-05-26 01:10:34 +0000248 ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000249 ldr r2, =0x0C548 @ CLK_DIV_FSYS2
250 str r1, [r0, r2]
251
252 /* MMC4 */
253 ldr r1, =0x000f /* 800(MPLL) / (15 + 1) */
254 ldr r2, =0x0C54C @ CLK_DIV_FSYS3
255 str r1, [r0, r2]
256
257 /* wait ?us */
258 mov r1, #0x10000
2594: subs r1, r1, #1
260 bne 4b
261
262 /*
263 * CLK_DIV_PERIL0:
264 *
265 * UART5_RATIO[20] 8
266 * UART4_RATIO[16] 8
267 * UART3_RATIO[12] 8
268 * UART2_RATIO[8] 8
269 * UART1_RATIO[4] 8
270 * UART0_RATIO[0] 8
271 */
272 ldr r1, =0x774777
273 ldr r2, =0x0C550 @CLK_DIV_PERIL0_OFFSET
274 str r1, [r0, r2]
275
276 /* SLIMBUS: ???, PWM */
277 ldr r1, =0x8
278 ldr r2, =0x0C55C @ CLK_DIV_PERIL3
279 str r1, [r0, r2]
280
281 /* Set PLL locktime */
282 ldr r1, =0x01C20
283 ldr r2, =0x014000 @APLL_LOCK_OFFSET
284 str r1, [r0, r2]
285 ldr r1, =0x01C20
286 ldr r2, =0x014008 @MPLL_LOCK_OFFSET
287 str r1, [r0, r2]
288 ldr r1, =0x01C20
289 ldr r2, =0x0C010 @EPLL_LOCK_OFFSET
290 str r1, [r0, r2]
291 ldr r1, =0x01C20
292 ldr r2, =0x0C020 @VPLL_LOCK_OFFSET
293 str r1, [r0, r2]
294
295 /*
296 * APLL_CON1:
297 *
298 * APLL_AFC_ENB[31] 0x1
299 * APLL_AFC[0] 0xC
300 */
301 ldr r1, =0x8000000C
302 ldr r2, =0x014104 @APLL_CON1_OFFSET
303 str r1, [r0, r2]
304
305 /*
306 * APLL_CON0:
307 *
308 * APLL_MDIV[16] 0xFA
309 * APLL_PDIV[8] 0x6
310 * APLL_SDIV[0] 0x1
311 */
312 ldr r1, =0x80FA0601
313 ldr r2, =0x014100 @APLL_CON0_OFFSET
314 str r1, [r0, r2]
315
316 /*
317 * MPLL_CON1:
318 *
319 * MPLL_AFC_ENB[31] 0x1
320 * MPLL_AFC[0] 0x1C
321 */
322 ldr r1, =0x0000001C
323 ldr r2, =0x01410C @MPLL_CON1_OFFSET
324 str r1, [r0, r2]
325
326 /*
327 * MPLL_CON0:
328 *
329 * MPLL_MDIV[16] 0xC8
330 * MPLL_PDIV[8] 0x6
331 * MPLL_SDIV[0] 0x1
332 */
333 ldr r1, =0x80C80601
334 ldr r2, =0x014108 @MPLL_CON0_OFFSET
335 str r1, [r0, r2]
336
337 /* EPLL */
338 ldr r1, =0x0
339 ldr r2, =0x0C114 @EPLL_CON1_OFFSET
340 str r1, [r0, r2]
341
342 /*
343 * EPLL_CON0:
344 *
345 * EPLL_MDIV[16] 0x30
346 * EPLL_PDIV[8] 0x3
347 * EPLL_SDIV[0] 0x2
348 */
349 ldr r1, =0x80300302
350 ldr r2, =0x0C110 @EPLL_CON0_OFFSET
351 str r1, [r0, r2]
352
353 /*
354 * VPLL_CON1:
355 *
356 * VPLL_MRR[24] 0x11
357 * VPLL_MFR[16] 0x0
358 * VPLL_K[0] 0x400
359 */
360 ldr r1, =0x11000400
361 ldr r2, =0x0C124 @VPLL_CON1_OFFSET
362 str r1, [r0, r2]
363
364 /*
365 * VPLL_CON0:
366 *
367 * VPLL_MDIV[16] 0x35
368 * VPLL_PDIV[8] 0x3
369 * VPLL_SDIV[0] 0x2
370 */
371 ldr r1, =0x80350302
372 ldr r2, =0x0C120 @VPLL_CON0_OFFSET
373 str r1, [r0, r2]
374
375 /* wait ?us */
376 mov r1, #0x30000
3773: subs r1, r1, #1
378 bne 3b
379
380 pop {pc}
381/*
382 * uart_asm_init: Initialize UART in asm mode, 115200bps fixed.
383 * void uart_asm_init(void)
384 */
385 .globl uart_asm_init
386uart_asm_init:
387
388 /* setup UART0-UART3 GPIOs (part1) */
389 mov r0, r7
390 ldr r1, =0x22222222
391 str r1, [r0, #0x00] @ S5PC210_GPIO_A0_OFFSET
392 ldr r1, =0x00222222
393 str r1, [r0, #0x20] @ S5PC210_GPIO_A1_OFFSET
394
395 ldr r0, =S5PC210_UART_BASE
396 add r0, r0, #S5PC210_DEFAULT_UART_OFFSET
397
398 ldr r1, =0x3C5
399 str r1, [r0, #0x4]
400 ldr r1, =0x111
401 str r1, [r0, #0x8]
402 ldr r1, =0x3
403 str r1, [r0, #0x0]
404 ldr r1, =0x35
405 str r1, [r0, #0x28]
406 ldr r1, =0x4
407 str r1, [r0, #0x2c]
408
409 mov pc, lr
410 nop
411 nop
412 nop
413
414/* Setting TZPC[TrustZone Protection Controller] */
415tzpc_init:
416 ldr r0, =0x10110000
417 mov r1, #0x0
418 str r1, [r0]
419 mov r1, #0xff
420 str r1, [r0, #0x0804]
421 str r1, [r0, #0x0810]
422 str r1, [r0, #0x081C]
423 str r1, [r0, #0x0828]
424
425 ldr r0, =0x10120000
426 mov r1, #0x0
427 str r1, [r0]
428 mov r1, #0xff
429 str r1, [r0, #0x0804]
430 str r1, [r0, #0x0810]
431 str r1, [r0, #0x081C]
432 str r1, [r0, #0x0828]
433
434 ldr r0, =0x10130000
435 mov r1, #0x0
436 str r1, [r0]
437 mov r1, #0xff
438 str r1, [r0, #0x0804]
439 str r1, [r0, #0x0810]
440 str r1, [r0, #0x081C]
441 str r1, [r0, #0x0828]
442
443 ldr r0, =0x10140000
444 mov r1, #0x0
445 str r1, [r0]
446 mov r1, #0xff
447 str r1, [r0, #0x0804]
448 str r1, [r0, #0x0810]
449 str r1, [r0, #0x081C]
450 str r1, [r0, #0x0828]
451
452 ldr r0, =0x10150000
453 mov r1, #0x0
454 str r1, [r0]
455 mov r1, #0xff
456 str r1, [r0, #0x0804]
457 str r1, [r0, #0x0810]
458 str r1, [r0, #0x081C]
459 str r1, [r0, #0x0828]
460
461 ldr r0, =0x10160000
462 mov r1, #0x0
463 str r1, [r0]
464 mov r1, #0xff
465 str r1, [r0, #0x0804]
466 str r1, [r0, #0x0810]
467 str r1, [r0, #0x081C]
468 str r1, [r0, #0x0828]
469
470 mov pc, lr