Bin Meng | 53a184b | 2019-07-18 00:34:31 -0700 | [diff] [blame] | 1 | .. SPDX-License-Identifier: GPL-2.0+ |
| 2 | |
| 3 | M68K / ColdFire |
| 4 | =============== |
| 5 | |
| 6 | History |
| 7 | ------- |
Angelo Dureghello | 5c136c9 | 2023-04-05 01:19:03 +0200 | [diff] [blame] | 8 | * November 02, 2017 Angelo Dureghello <angelo@kernel-space.org> |
Bin Meng | 53a184b | 2019-07-18 00:34:31 -0700 | [diff] [blame] | 9 | * August 08, 2005 Jens Scharsig <esw@bus-elektronik.de> |
| 10 | MCF5282 implementation without preloader |
| 11 | * January 12, 2004 <josef.baumgartner@telex.de> |
| 12 | |
| 13 | This file contains status information for the port of U-Boot to the |
| 14 | Motorola ColdFire series of CPUs. |
| 15 | |
| 16 | Overview |
| 17 | -------- |
| 18 | |
| 19 | The ColdFire instruction set is "assembly source" compatible but an evolution |
| 20 | of the original 68000 instruction set. Some not much used instructions has |
| 21 | been removed. The instructions are only 16, 32, or 48 bits long, a |
| 22 | simplification compared to the 68000 series. |
| 23 | |
| 24 | Bernhard Kuhn ported U-Boot 0.4.0 to the Motorola ColdFire architecture. |
| 25 | The patches of Bernhard support the MCF5272 and MCF5282. A great disadvantage |
| 26 | of these patches was that they needed a pre-bootloader to start U-Boot. |
| 27 | Because of this, a new port was created which no longer needs a first stage |
| 28 | booter. |
| 29 | |
| 30 | Thanks mainly to Freescale but also to several other contributors, U-Boot now |
| 31 | supports nearly the entire range of ColdFire processors and their related |
| 32 | development boards. |
| 33 | |
| 34 | |
| 35 | Supported CPU families |
| 36 | ---------------------- |
| 37 | |
Tom Rini | caed6ff | 2020-05-26 14:36:53 -0400 | [diff] [blame] | 38 | Please "make menuconfig" and select "m68k" or check arch/m68k/cpu to see the |
Bin Meng | 53a184b | 2019-07-18 00:34:31 -0700 | [diff] [blame] | 39 | currently supported processor and families. |
| 40 | |
| 41 | |
| 42 | Supported boards |
| 43 | ---------------- |
| 44 | |
| 45 | U-Boot supports actually more than 40 ColdFire based boards. |
| 46 | Board configuration can be done trough include/configs/<boardname>.h but the |
| 47 | current recommended method is to use the new and more friendly approach as |
| 48 | the "make menuconfig" way, very similar to the Linux way. |
| 49 | |
| 50 | To know details as memory map, build targets, default setup, etc, of a |
| 51 | specific board please check: |
| 52 | |
| 53 | * include/configs/<boardname>.h |
| 54 | |
| 55 | and/or |
| 56 | |
| 57 | * configs/<boardname>_defconfig |
| 58 | |
| 59 | It is possible to build all ColdFire boards in a single command-line command, |
| 60 | from u-boot root directory, as:: |
| 61 | |
| 62 | ./tools/buildman/buildman m68k |
| 63 | |
| 64 | Build U-Boot for a specific board |
| 65 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 66 | |
| 67 | A bash script similar to the one below may be used: |
| 68 | |
| 69 | .. code-block:: shell |
| 70 | |
| 71 | #!/bin/bash |
| 72 | |
| 73 | export CROSS_COMPILE=/opt/toolchains/m68k/gcc-4.9.0-nolibc/bin/m68k-linux- |
| 74 | |
Tom Rini | 7ab2f5f | 2021-05-14 21:34:10 -0400 | [diff] [blame] | 75 | board=M5249EVB |
Bin Meng | 53a184b | 2019-07-18 00:34:31 -0700 | [diff] [blame] | 76 | |
| 77 | make distclean |
Tom Rini | caed6ff | 2020-05-26 14:36:53 -0400 | [diff] [blame] | 78 | make ${board}_defconfig |
| 79 | make KBUILD_VERBOSE=1 |
Bin Meng | 53a184b | 2019-07-18 00:34:31 -0700 | [diff] [blame] | 80 | |
| 81 | |
| 82 | Adopted toolchains |
| 83 | ------------------ |
| 84 | |
| 85 | Please check: |
| 86 | https://www.denx.de/wiki/U-Boot/ColdFireNotes |
| 87 | |
| 88 | |
| 89 | ColdFire specific configuration options/settings |
| 90 | ------------------------------------------------ |
| 91 | |
| 92 | Configuration to use a pre-loader |
| 93 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 94 | |
| 95 | If U-Boot should be loaded to RAM and started by a pre-loader |
Tom Rini | b73cd90 | 2022-12-02 16:42:36 -0500 | [diff] [blame] | 96 | CONFIG_MONITOR_IS_IN_RAM must be enabled. If it is enabled the |
Bin Meng | 53a184b | 2019-07-18 00:34:31 -0700 | [diff] [blame] | 97 | initial vector table and basic processor initialization will not |
| 98 | be compiled in. The start address of U-Boot must be adjusted in |
Tom Rini | b73cd90 | 2022-12-02 16:42:36 -0500 | [diff] [blame] | 99 | the boards defconfig file (CONFIG_SYS_MONITOR_BASE) and Makefile |
Simon Glass | 72cc538 | 2022-10-20 18:22:39 -0600 | [diff] [blame] | 100 | (CONFIG_TEXT_BASE) to the load address. |
Bin Meng | 53a184b | 2019-07-18 00:34:31 -0700 | [diff] [blame] | 101 | |
| 102 | ColdFire CPU specific options/settings |
| 103 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 104 | |
| 105 | To specify a CPU model, some defines shoudl be used, i.e.: |
| 106 | |
| 107 | CONFIG_MCF52x2: |
| 108 | defined for all MCF52x2 CPUs |
| 109 | CONFIG_M5272: |
| 110 | defined for all Motorola MCF5272 CPUs |
| 111 | |
| 112 | Other options, generally set inside include/configs/<boardname>.h, they may |
| 113 | apply to one or more cpu for the ColdFire family: |
| 114 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 115 | CFG_SYS_MBAR: |
Bin Meng | 53a184b | 2019-07-18 00:34:31 -0700 | [diff] [blame] | 116 | defines the base address of the MCF5272 configuration registers |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 117 | CFG_SYS_SCR: |
Bin Meng | 53a184b | 2019-07-18 00:34:31 -0700 | [diff] [blame] | 118 | defines the contents of the System Configuration Register |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 119 | CFG_SYS_SPR: |
Bin Meng | 53a184b | 2019-07-18 00:34:31 -0700 | [diff] [blame] | 120 | defines the contents of the System Protection Register |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 121 | CFG_SYS_MFD: |
Bin Meng | 53a184b | 2019-07-18 00:34:31 -0700 | [diff] [blame] | 122 | defines the PLL Multiplication Factor Divider |
| 123 | (see table 9-4 of MCF user manual) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 124 | CFG_SYS_RFD: |
Bin Meng | 53a184b | 2019-07-18 00:34:31 -0700 | [diff] [blame] | 125 | defines the PLL Reduce Frequency Devider |
| 126 | (see table 9-4 of MCF user manual) |
| 127 | CONFIG_SYS_CSx_BASE: |
| 128 | defines the base address of chip select x |
| 129 | CONFIG_SYS_CSx_SIZE: |
| 130 | defines the memory size (address range) of chip select x |
| 131 | CONFIG_SYS_CSx_WIDTH: |
| 132 | defines the bus with of chip select x |
| 133 | CONFIG_SYS_CSx_MASK: |
| 134 | defines the mask for the related chip select x |
| 135 | CONFIG_SYS_CSx_RO: |
| 136 | if set to 0 chip select x is read/write else chip select is read only |
| 137 | CONFIG_SYS_CSx_WS: |
| 138 | defines the number of wait states of chip select x |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 139 | CFG_SYS_CACHE_ICACR: |
Bin Meng | 53a184b | 2019-07-18 00:34:31 -0700 | [diff] [blame] | 140 | cache-related registers config |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 141 | CFG_SYS_CACHE_DCACR: |
Bin Meng | 53a184b | 2019-07-18 00:34:31 -0700 | [diff] [blame] | 142 | cache-related registers config |
| 143 | CONFIG_SYS_CACHE_ACRX: |
| 144 | cache-related registers config |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 145 | CFG_SYS_SDRAM_BASE: |
Bin Meng | 53a184b | 2019-07-18 00:34:31 -0700 | [diff] [blame] | 146 | SDRAM config for SDRAM controller-specific registers |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 147 | CFG_SYS_SDRAM_SIZE: |
Bin Meng | 53a184b | 2019-07-18 00:34:31 -0700 | [diff] [blame] | 148 | SDRAM config for SDRAM controller-specific registers |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 149 | CFG_SYS_SDRAM_BASEX: |
Bin Meng | 53a184b | 2019-07-18 00:34:31 -0700 | [diff] [blame] | 150 | SDRAM config for SDRAM controller-specific registers |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 151 | CFG_SYS_SDRAM_CFG1: |
Bin Meng | 53a184b | 2019-07-18 00:34:31 -0700 | [diff] [blame] | 152 | SDRAM config for SDRAM controller-specific registers |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 153 | CFG_SYS_SDRAM_CFG2: |
Bin Meng | 53a184b | 2019-07-18 00:34:31 -0700 | [diff] [blame] | 154 | SDRAM config for SDRAM controller-specific registers |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 155 | CFG_SYS_SDRAM_CTRL: |
Bin Meng | 53a184b | 2019-07-18 00:34:31 -0700 | [diff] [blame] | 156 | SDRAM config for SDRAM controller-specific registers |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 157 | CFG_SYS_SDRAM_MODE: |
Bin Meng | 53a184b | 2019-07-18 00:34:31 -0700 | [diff] [blame] | 158 | SDRAM config for SDRAM controller-specific registers |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 159 | CFG_SYS_SDRAM_EMOD: |
Bin Meng | 53a184b | 2019-07-18 00:34:31 -0700 | [diff] [blame] | 160 | SDRAM config for SDRAM controller-specific registers, please |
| 161 | see arch/m68k/cpu/<specific_cpu>/start.S files to see how |
| 162 | these options are used. |
| 163 | CONFIG_MCFUART: |
| 164 | defines enabling of ColdFire UART driver |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 165 | CFG_SYS_UART_PORT: |
Bin Meng | 53a184b | 2019-07-18 00:34:31 -0700 | [diff] [blame] | 166 | defines the UART port to be used (only a single UART can be actually enabled) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 167 | CFG_SYS_SBFHDR_SIZE: |
Bin Meng | 53a184b | 2019-07-18 00:34:31 -0700 | [diff] [blame] | 168 | size of the prepended SBF header, if any |