Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright 2021 Gateworks Corporation |
| 4 | */ |
| 5 | |
| 6 | #ifndef __IMX8MM_VENICE_H |
| 7 | #define __IMX8MM_VENICE_H |
| 8 | |
| 9 | #include <asm/arch/imx-regs.h> |
| 10 | #include <linux/sizes.h> |
| 11 | |
| 12 | #define CONFIG_SPL_MAX_SIZE (148 * 1024) |
| 13 | #define CONFIG_SYS_MONITOR_LEN SZ_512K |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 14 | #define CONFIG_SYS_UBOOT_BASE \ |
| 15 | (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) |
| 16 | |
| 17 | #ifdef CONFIG_SPL_BUILD |
| 18 | #define CONFIG_SPL_STACK 0x920000 |
| 19 | #define CONFIG_SPL_BSS_START_ADDR 0x910000 |
Tim Harvey | e122b1c | 2021-03-08 13:52:36 -0800 | [diff] [blame] | 20 | #define CONFIG_SPL_BSS_MAX_SIZE SZ_8K |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 21 | #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 |
Tim Harvey | e122b1c | 2021-03-08 13:52:36 -0800 | [diff] [blame] | 22 | #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_1M |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 23 | |
| 24 | /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ |
| 25 | #define CONFIG_MALLOC_F_ADDR 0x930000 |
| 26 | /* For RAW image gives a error info not panic */ |
| 27 | #define CONFIG_SPL_ABORT_ON_RAW_IMAGE |
| 28 | |
| 29 | #endif |
| 30 | |
| 31 | #define MEM_LAYOUT_ENV_SETTINGS \ |
| 32 | "fdt_addr_r=0x44000000\0" \ |
| 33 | "kernel_addr_r=0x42000000\0" \ |
| 34 | "ramdisk_addr_r=0x46400000\0" \ |
| 35 | "scriptaddr=0x46000000\0" |
| 36 | |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 37 | /* Enable Distro Boot */ |
| 38 | #ifndef CONFIG_SPL_BUILD |
| 39 | #define BOOT_TARGET_DEVICES(func) \ |
| 40 | func(MMC, mmc, 1) \ |
| 41 | func(MMC, mmc, 2) \ |
| 42 | func(DHCP, dhcp, na) |
| 43 | #include <config_distro_bootcmd.h> |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 44 | #else |
| 45 | #define BOOTENV |
| 46 | #endif |
| 47 | |
| 48 | /* Initial environment variables */ |
| 49 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 50 | BOOTENV \ |
| 51 | MEM_LAYOUT_ENV_SETTINGS \ |
| 52 | "script=boot.scr\0" \ |
| 53 | "bootm_size=0x10000000\0" \ |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 54 | "dev=2\0" \ |
| 55 | "preboot=gsc wd-disable\0" \ |
| 56 | "console=ttymxc1,115200\0" \ |
| 57 | "update_firmware=" \ |
| 58 | "tftpboot $loadaddr $image && " \ |
| 59 | "setexpr blkcnt $filesize + 0x1ff && " \ |
| 60 | "setexpr blkcnt $blkcnt / 0x200 && " \ |
| 61 | "mmc dev $dev && " \ |
| 62 | "mmc write $loadaddr 0x42 $blkcnt\0" \ |
Tim Harvey | 145e3a8 | 2022-02-18 15:20:17 -0800 | [diff] [blame] | 63 | "loadfdt=" \ |
| 64 | "if $fsload $fdt_addr_r $dir/$fdt_file1; " \ |
| 65 | "then echo loaded $fdt_file1; " \ |
| 66 | "elif $fsload $fdt_addr_r $dir/$fdt_file2; " \ |
| 67 | "then echo loaded $fdt_file2; " \ |
| 68 | "elif $fsload $fdt_addr_r $dir/$fdt_file3; " \ |
| 69 | "then echo loaded $fdt_file3; " \ |
| 70 | "elif $fsload $fdt_addr_r $dir/$fdt_file4; " \ |
| 71 | "then echo loaded $fdt_file4; " \ |
| 72 | "elif $fsload $fdt_addr_r $dir/$fdt_file5; " \ |
| 73 | "then echo loaded $fdt_file5; " \ |
| 74 | "fi\0" \ |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 75 | "boot_net=" \ |
Tim Harvey | 145e3a8 | 2022-02-18 15:20:17 -0800 | [diff] [blame] | 76 | "setenv fsload tftpboot; " \ |
| 77 | "run loadfdt && tftpboot $kernel_addr_r $dir/Image && " \ |
| 78 | "booti $kernel_addr_r - $fdt_addr_r\0" \ |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 79 | "update_rootfs=" \ |
| 80 | "tftpboot $loadaddr $image && " \ |
| 81 | "gzwrite mmc $dev $loadaddr $filesize 100000 1000000\0" \ |
| 82 | "update_all=" \ |
| 83 | "tftpboot $loadaddr $image && " \ |
| 84 | "gzwrite mmc $dev $loadaddr $filesize\0" \ |
| 85 | "erase_env=mmc dev $dev; mmc erase 0x7f08 0x40\0" |
| 86 | |
| 87 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 |
| 88 | #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M |
| 89 | #define CONFIG_SYS_INIT_SP_OFFSET \ |
| 90 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| 91 | #define CONFIG_SYS_INIT_SP_ADDR \ |
| 92 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
| 93 | |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 94 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
| 95 | |
| 96 | /* SDRAM configuration */ |
| 97 | #define PHYS_SDRAM 0x40000000 |
Tim Harvey | 56c5e31 | 2022-03-30 13:39:02 -0700 | [diff] [blame] | 98 | #define PHYS_SDRAM_SIZE SZ_4G |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 99 | #define CONFIG_SYS_BOOTM_LEN SZ_256M |
| 100 | |
| 101 | /* UART */ |
| 102 | #define CONFIG_MXC_UART_BASE UART2_BASE_ADDR |
| 103 | |
| 104 | /* Monitor Command Prompt */ |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 105 | #define CONFIG_SYS_CBSIZE SZ_2K |
| 106 | #define CONFIG_SYS_MAXARGS 64 |
| 107 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| 108 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
| 109 | sizeof(CONFIG_SYS_PROMPT) + 16) |
| 110 | |
| 111 | /* USDHC */ |
| 112 | #define CONFIG_SYS_FSL_USDHC_NUM 2 |
| 113 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 114 | |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 115 | /* FEC */ |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 116 | #define CONFIG_FEC_MXC_PHYADDR 0 |
| 117 | #define FEC_QUIRK_ENET_MAC |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 118 | |
| 119 | #endif |