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git01.mediatek.com / filogic / uboot / bebd282446306e3adfea2144af472e87856955d8 / . / configs / ls2080aqds_SECURE_BOOT_defconfig
blob: dfe180dfd27ad88cad678d867f7de0eb8260ced9 [file] [log] [blame]
Saksham Jainc0c38d22016-03-23 16:24:35 +0530[diff] [blame]1CONFIG_ARM=y
Tom Rini3eea5772020-05-08 09:08:39 -0400[diff] [blame]2CONFIG_GIC_V3_ITS=y
Saksham Jainc0c38d22016-03-23 16:24:35 +0530[diff] [blame]3CONFIG_TARGET_LS2080AQDS=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]4CONFIG_SYS_TEXT_BASE=0x30100000
Tom Rinie25a03a2021-11-01 12:19:22 +0000[diff] [blame]5CONFIG_SYS_MALLOC_LEN=0x202000
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]6CONFIG_NR_DRAM_BANKS=3
Tom Rini5cd7ece2019-11-18 20:02:10 -0500[diff] [blame]7CONFIG_ENV_SIZE=0x2000
Tom Rini47dece32020-04-28 16:15:47 -0400[diff] [blame]8CONFIG_NXP_ESBC=y
Tom Rini84610272020-07-28 08:46:52 -0400[diff] [blame]9CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
Tom Rini2c082ab2021-07-26 21:10:37 -0400[diff] [blame]10CONFIG_FSL_USE_PCA9547_MUX=y
Tom Rinie24547a2022-03-30 18:07:32 -0400[diff] [blame]11CONFIG_FSL_QIXIS=y
12# CONFIG_QIXIS_I2C_ACCESS is not set
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]13CONFIG_FSL_LS_PPA=y
Tom Rinic9285bf2019-04-29 15:54:04 -0400[diff] [blame]14CONFIG_AHCI=y
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]15# CONFIG_SYS_MALLOC_F is not set
Alper Nebi Yasak2beb0f42022-01-29 18:25:30 +0300[diff] [blame]16CONFIG_REMAKE_ELF=y
Tom Rini5ca768d2022-01-24 21:08:41 +0000[diff] [blame]17CONFIG_MP=y
Saksham Jainc0c38d22016-03-23 16:24:35 +0530[diff] [blame]18CONFIG_FIT_VERBOSE=y
19CONFIG_OF_BOARD_SETUP=y
20CONFIG_OF_STDOUT_VIA_ALIAS=y
Tom Rini8c70baa2021-12-14 13:36:40 -0500[diff] [blame]21CONFIG_DYNAMIC_SYS_CLK_FREQ=y
Heiko Schocher0b368b12016-06-07 08:31:14 +0200[diff] [blame]22CONFIG_BOOTDELAY=10
Sam Protsenkobd7bffe2017-08-14 20:22:17 +0300[diff] [blame]23CONFIG_USE_BOOTARGS=y
24CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
Tom Rini5ddf1722021-11-10 09:11:40 -0500[diff] [blame]25CONFIG_BOOTCOMMAND="fsl_mc apply dpl 0x580d00000 && cp.b $kernel_start $kernel_load $kernel_size && bootm $kernel_load"
Tom Rini356c6742022-03-18 08:38:20 -0400[diff] [blame]26CONFIG_RESET_PHY_R=y
Tuomas Tynkkynen28d56bd2017-10-08 21:48:01 +0300[diff] [blame]27CONFIG_CMD_IMLS=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]28CONFIG_CMD_GREPENV=y
Simon Glass4590d4e2017-05-17 03:25:10 -0600[diff] [blame]29CONFIG_CMD_EEPROM=y
Tom Rinifaed5672021-08-17 17:59:45 -0400[diff] [blame]30CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
31CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]32CONFIG_CMD_GPT=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]33CONFIG_CMD_I2C=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]34CONFIG_CMD_MMC=y
Tom Rini00448d22017-07-28 21:31:42 -0400[diff] [blame]35CONFIG_CMD_NAND=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]36CONFIG_CMD_PCI=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]37CONFIG_CMD_USB=y
Saksham Jainc0c38d22016-03-23 16:24:35 +0530[diff] [blame]38# CONFIG_CMD_SETEXPR is not set
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]39CONFIG_CMD_CACHE=y
Chris Packham3e257df2017-04-29 15:20:28 +1200[diff] [blame]40CONFIG_CMD_DATE=y
Patrick Delaunay21d3bce2017-01-27 11:00:38 +0100[diff] [blame]41# CONFIG_ISO_PARTITION is not set
Saksham Jainc0c38d22016-03-23 16:24:35 +0530[diff] [blame]42CONFIG_OF_CONTROL=y
Adam Ford710966e2020-07-03 06:48:56 -0500[diff] [blame]43CONFIG_ENV_OVERWRITE=y
Tom Rinife586752022-03-11 09:12:07 -0500[diff] [blame]44CONFIG_USE_ETHPRIME=y
45CONFIG_ETHPRIME="DPMAC1@xgmii"
Saksham Jainc0c38d22016-03-23 16:24:35 +0530[diff] [blame]46CONFIG_NET_RANDOM_ETHADDR=y
47CONFIG_DM=y
Simon Glass701ef062022-01-31 07:49:33 -0700[diff] [blame]48CONFIG_SATA=y
Peng Ma1c4bf2f2019-01-30 19:17:44 +0800[diff] [blame]49CONFIG_SATA_CEVA=y
Tom Rinif7246c22021-08-21 13:50:17 -0400[diff] [blame]50CONFIG_DYNAMIC_DDR_CLK_FREQ=y
Tom Rini3210bdc2022-03-30 18:07:31 -0400[diff] [blame]51CONFIG_DIMM_SLOTS_PER_CTLR=2
Tom Rini468c2d52021-08-21 13:50:18 -0400[diff] [blame]52CONFIG_DDR_ECC=y
53CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
Tom Rini52b2e262021-08-18 23:12:24 -0400[diff] [blame]54CONFIG_SYS_I2C_LEGACY=y
Tom Rinifaed5672021-08-17 17:59:45 -0400[diff] [blame]55CONFIG_SYS_I2C_EEPROM_ADDR=0x57
Mario Six41d7d972018-03-28 14:38:19 +0200[diff] [blame]56CONFIG_FSL_ESDHC=y
Tom Rinie799f922019-12-04 17:18:38 -0500[diff] [blame]57CONFIG_MTD=y
Masahiro Yamada8cea9b52017-02-11 22:43:54 +0900[diff] [blame]58CONFIG_MTD_NOR_FLASH=y
Adam Ford76da1b22018-10-14 15:10:50 -0500[diff] [blame]59CONFIG_FLASH_CFI_DRIVER=y
60CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
61CONFIG_SYS_FLASH_CFI=y
Patrick Delaunay1576abf2022-01-04 14:24:00 +0100[diff] [blame]62CONFIG_SYS_MAX_FLASH_BANKS=2
Tom Rinie799f922019-12-04 17:18:38 -0500[diff] [blame]63CONFIG_MTD_RAW_NAND=y
Tom Rinia73788c2021-09-22 14:50:37 -0400[diff] [blame]64CONFIG_NAND_FSL_IFC=y
Tom Rinifdae0072021-09-22 14:50:34 -0400[diff] [blame]65CONFIG_SYS_NAND_ONFI_DETECTION=y
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]66CONFIG_DM_SPI_FLASH=y
Tom Rinid391d8b2021-12-11 14:55:51 -0500[diff] [blame]67CONFIG_SPI_FLASH_EON=y
68CONFIG_SPI_FLASH_STMICRO=y
69CONFIG_SPI_FLASH_SST=y
Alexandru Gagniucd83e98c2017-08-01 17:19:59 -0700[diff] [blame]70CONFIG_PHYLIB=y
Tom Rini5d154192020-04-24 15:35:53 -0400[diff] [blame]71CONFIG_PHYLIB_10G=y
72CONFIG_PHY_REALTEK=y
73CONFIG_PHY_TERANETICS=y
74CONFIG_PHY_VITESSE=y
Tom Rinica22e962017-08-07 22:00:34 -0400[diff] [blame]75CONFIG_PHY_GIGE=y
Saksham Jainc0c38d22016-03-23 16:24:35 +0530[diff] [blame]76CONFIG_E1000=y
Adam Ford53705472018-07-20 23:03:57 -0500[diff] [blame]77CONFIG_MII=y
Mark Kettenisf8463d62022-01-22 20:38:11 +0100[diff] [blame]78CONFIG_NVME_PCI=y
Tom Rini9834b902017-03-13 13:48:42 -0400[diff] [blame]79CONFIG_PCI=y
Tom Rini9834b902017-03-13 13:48:42 -0400[diff] [blame]80CONFIG_DM_PCI_COMPAT=y
Hou Zhiqiang02f1f062020-07-09 23:31:42 +0800[diff] [blame]81CONFIG_PCIE_LAYERSCAPE_RC=y
Tom Rinid391d8b2021-12-11 14:55:51 -0500[diff] [blame]82CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
Peng Ma1c4bf2f2019-01-30 19:17:44 +0800[diff] [blame]83CONFIG_DM_SCSI=y
Saksham Jainc0c38d22016-03-23 16:24:35 +0530[diff] [blame]84CONFIG_SYS_NS16550=y
Adam Ford4e96ff82018-04-15 13:51:26 -0400[diff] [blame]85CONFIG_SPI=y
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]86CONFIG_DM_SPI=y
Saksham Jainc0c38d22016-03-23 16:24:35 +0530[diff] [blame]87CONFIG_FSL_DSPI=y
Masahiro Yamada58d00232016-06-04 07:35:03 +0900[diff] [blame]88CONFIG_USB=y
89CONFIG_USB_XHCI_HCD=y
Masahiro Yamadad3b72ca2016-06-04 07:35:04 +0900[diff] [blame]90CONFIG_USB_XHCI_DWC3=y
Saksham Jainc0c38d22016-03-23 16:24:35 +0530[diff] [blame]91CONFIG_RSA=y
Tom Rinia5c4d402017-03-01 16:51:58 -0500[diff] [blame]92CONFIG_RSA_SOFTWARE_EXP=y