Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Aneesh V | 960f5c0 | 2011-06-16 23:30:47 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2010 |
| 4 | * Texas Instruments, <www.ti.com> |
| 5 | * Aneesh V <aneesh@ti.com> |
Aneesh V | 960f5c0 | 2011-06-16 23:30:47 +0000 | [diff] [blame] | 6 | */ |
Simon Glass | 6333448 | 2019-11-14 12:57:39 -0700 | [diff] [blame] | 7 | #include <cpu_func.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 8 | #include <asm/cache.h> |
Aneesh V | 960f5c0 | 2011-06-16 23:30:47 +0000 | [diff] [blame] | 9 | #include <linux/types.h> |
| 10 | #include <common.h> |
| 11 | #include <asm/armv7.h> |
| 12 | #include <asm/utils.h> |
| 13 | |
Hans de Goede | ba3bf9b | 2016-04-09 13:53:49 +0200 | [diff] [blame] | 14 | #define ARMV7_DCACHE_INVAL_RANGE 1 |
| 15 | #define ARMV7_DCACHE_CLEAN_INVAL_RANGE 2 |
Aneesh V | 960f5c0 | 2011-06-16 23:30:47 +0000 | [diff] [blame] | 16 | |
Trevor Woerner | 43ec7e0 | 2019-05-03 09:41:00 -0400 | [diff] [blame] | 17 | #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) |
Hans de Goede | 076e841 | 2016-04-09 13:53:48 +0200 | [diff] [blame] | 18 | |
| 19 | /* Asm functions from cache_v7_asm.S */ |
| 20 | void v7_flush_dcache_all(void); |
Hans de Goede | ba3bf9b | 2016-04-09 13:53:49 +0200 | [diff] [blame] | 21 | void v7_invalidate_dcache_all(void); |
Hans de Goede | 076e841 | 2016-04-09 13:53:48 +0200 | [diff] [blame] | 22 | |
Aneesh V | 960f5c0 | 2011-06-16 23:30:47 +0000 | [diff] [blame] | 23 | static u32 get_ccsidr(void) |
| 24 | { |
| 25 | u32 ccsidr; |
| 26 | |
| 27 | /* Read current CP15 Cache Size ID Register */ |
| 28 | asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr)); |
| 29 | return ccsidr; |
| 30 | } |
| 31 | |
Thierry Reding | 0c59738 | 2014-08-26 17:34:20 +0200 | [diff] [blame] | 32 | static void v7_dcache_clean_inval_range(u32 start, u32 stop, u32 line_len) |
Aneesh V | 960f5c0 | 2011-06-16 23:30:47 +0000 | [diff] [blame] | 33 | { |
| 34 | u32 mva; |
| 35 | |
| 36 | /* Align start to cache line boundary */ |
| 37 | start &= ~(line_len - 1); |
| 38 | for (mva = start; mva < stop; mva = mva + line_len) { |
| 39 | /* DCCIMVAC - Clean & Invalidate data cache by MVA to PoC */ |
| 40 | asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva)); |
| 41 | } |
| 42 | } |
| 43 | |
| 44 | static void v7_dcache_inval_range(u32 start, u32 stop, u32 line_len) |
| 45 | { |
| 46 | u32 mva; |
| 47 | |
Simon Glass | b7ba957 | 2016-06-19 19:43:02 -0600 | [diff] [blame] | 48 | if (!check_cache_range(start, stop)) |
| 49 | return; |
Aneesh V | 960f5c0 | 2011-06-16 23:30:47 +0000 | [diff] [blame] | 50 | |
| 51 | for (mva = start; mva < stop; mva = mva + line_len) { |
| 52 | /* DCIMVAC - Invalidate data cache by MVA to PoC */ |
| 53 | asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva)); |
| 54 | } |
| 55 | } |
| 56 | |
| 57 | static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op) |
| 58 | { |
| 59 | u32 line_len, ccsidr; |
| 60 | |
| 61 | ccsidr = get_ccsidr(); |
| 62 | line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >> |
| 63 | CCSIDR_LINE_SIZE_OFFSET) + 2; |
| 64 | /* Converting from words to bytes */ |
| 65 | line_len += 2; |
| 66 | /* converting from log2(linelen) to linelen */ |
| 67 | line_len = 1 << line_len; |
| 68 | |
| 69 | switch (range_op) { |
| 70 | case ARMV7_DCACHE_CLEAN_INVAL_RANGE: |
| 71 | v7_dcache_clean_inval_range(start, stop, line_len); |
| 72 | break; |
| 73 | case ARMV7_DCACHE_INVAL_RANGE: |
| 74 | v7_dcache_inval_range(start, stop, line_len); |
| 75 | break; |
| 76 | } |
| 77 | |
Aneesh V | 517912b | 2011-08-11 04:35:44 +0000 | [diff] [blame] | 78 | /* DSB to make sure the operation is complete */ |
Tom Rini | 3b787ef | 2016-08-01 18:54:53 -0400 | [diff] [blame] | 79 | dsb(); |
Aneesh V | 960f5c0 | 2011-06-16 23:30:47 +0000 | [diff] [blame] | 80 | } |
| 81 | |
| 82 | /* Invalidate TLB */ |
| 83 | static void v7_inval_tlb(void) |
| 84 | { |
| 85 | /* Invalidate entire unified TLB */ |
| 86 | asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0)); |
| 87 | /* Invalidate entire data TLB */ |
| 88 | asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0)); |
| 89 | /* Invalidate entire instruction TLB */ |
| 90 | asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0)); |
| 91 | /* Full system DSB - make sure that the invalidation is complete */ |
Tom Rini | 3b787ef | 2016-08-01 18:54:53 -0400 | [diff] [blame] | 92 | dsb(); |
Aneesh V | 960f5c0 | 2011-06-16 23:30:47 +0000 | [diff] [blame] | 93 | /* Full system ISB - make sure the instruction stream sees it */ |
Tom Rini | 3b787ef | 2016-08-01 18:54:53 -0400 | [diff] [blame] | 94 | isb(); |
Aneesh V | 960f5c0 | 2011-06-16 23:30:47 +0000 | [diff] [blame] | 95 | } |
| 96 | |
| 97 | void invalidate_dcache_all(void) |
| 98 | { |
Hans de Goede | ba3bf9b | 2016-04-09 13:53:49 +0200 | [diff] [blame] | 99 | v7_invalidate_dcache_all(); |
Aneesh V | 960f5c0 | 2011-06-16 23:30:47 +0000 | [diff] [blame] | 100 | |
| 101 | v7_outer_cache_inval_all(); |
| 102 | } |
| 103 | |
| 104 | /* |
| 105 | * Performs a clean & invalidation of the entire data cache |
| 106 | * at all levels |
| 107 | */ |
| 108 | void flush_dcache_all(void) |
| 109 | { |
Hans de Goede | 076e841 | 2016-04-09 13:53:48 +0200 | [diff] [blame] | 110 | v7_flush_dcache_all(); |
Aneesh V | 960f5c0 | 2011-06-16 23:30:47 +0000 | [diff] [blame] | 111 | |
| 112 | v7_outer_cache_flush_all(); |
| 113 | } |
| 114 | |
| 115 | /* |
| 116 | * Invalidates range in all levels of D-cache/unified cache used: |
| 117 | * Affects the range [start, stop - 1] |
| 118 | */ |
| 119 | void invalidate_dcache_range(unsigned long start, unsigned long stop) |
| 120 | { |
Marek Vasut | c28ad23 | 2015-07-27 22:34:17 +0200 | [diff] [blame] | 121 | check_cache_range(start, stop); |
| 122 | |
Aneesh V | 960f5c0 | 2011-06-16 23:30:47 +0000 | [diff] [blame] | 123 | v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE); |
| 124 | |
| 125 | v7_outer_cache_inval_range(start, stop); |
| 126 | } |
| 127 | |
| 128 | /* |
| 129 | * Flush range(clean & invalidate) from all levels of D-cache/unified |
| 130 | * cache used: |
| 131 | * Affects the range [start, stop - 1] |
| 132 | */ |
| 133 | void flush_dcache_range(unsigned long start, unsigned long stop) |
| 134 | { |
Marek Vasut | c28ad23 | 2015-07-27 22:34:17 +0200 | [diff] [blame] | 135 | check_cache_range(start, stop); |
| 136 | |
Aneesh V | 960f5c0 | 2011-06-16 23:30:47 +0000 | [diff] [blame] | 137 | v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE); |
| 138 | |
| 139 | v7_outer_cache_flush_range(start, stop); |
| 140 | } |
| 141 | |
| 142 | void arm_init_before_mmu(void) |
| 143 | { |
| 144 | v7_outer_cache_enable(); |
| 145 | invalidate_dcache_all(); |
| 146 | v7_inval_tlb(); |
| 147 | } |
| 148 | |
Simon Glass | a4f2079 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 149 | void mmu_page_table_flush(unsigned long start, unsigned long stop) |
| 150 | { |
| 151 | flush_dcache_range(start, stop); |
| 152 | v7_inval_tlb(); |
| 153 | } |
Trevor Woerner | 43ec7e0 | 2019-05-03 09:41:00 -0400 | [diff] [blame] | 154 | #else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ |
Aneesh V | 960f5c0 | 2011-06-16 23:30:47 +0000 | [diff] [blame] | 155 | void invalidate_dcache_all(void) |
| 156 | { |
| 157 | } |
| 158 | |
| 159 | void flush_dcache_all(void) |
| 160 | { |
| 161 | } |
| 162 | |
Daniel Allred | 4631f7d | 2016-06-27 09:19:16 -0500 | [diff] [blame] | 163 | void invalidate_dcache_range(unsigned long start, unsigned long stop) |
| 164 | { |
| 165 | } |
| 166 | |
| 167 | void flush_dcache_range(unsigned long start, unsigned long stop) |
| 168 | { |
| 169 | } |
| 170 | |
Aneesh V | 960f5c0 | 2011-06-16 23:30:47 +0000 | [diff] [blame] | 171 | void arm_init_before_mmu(void) |
| 172 | { |
| 173 | } |
| 174 | |
Simon Glass | a4f2079 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 175 | void mmu_page_table_flush(unsigned long start, unsigned long stop) |
| 176 | { |
| 177 | } |
| 178 | |
R Sricharan | 06396c1 | 2013-03-04 20:04:45 +0000 | [diff] [blame] | 179 | void arm_init_domains(void) |
| 180 | { |
| 181 | } |
Trevor Woerner | 43ec7e0 | 2019-05-03 09:41:00 -0400 | [diff] [blame] | 182 | #endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ |
Aneesh V | 960f5c0 | 2011-06-16 23:30:47 +0000 | [diff] [blame] | 183 | |
Trevor Woerner | 43ec7e0 | 2019-05-03 09:41:00 -0400 | [diff] [blame] | 184 | #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) |
Aneesh V | 960f5c0 | 2011-06-16 23:30:47 +0000 | [diff] [blame] | 185 | /* Invalidate entire I-cache and branch predictor array */ |
| 186 | void invalidate_icache_all(void) |
| 187 | { |
| 188 | /* |
| 189 | * Invalidate all instruction caches to PoU. |
| 190 | * Also flushes branch target cache. |
| 191 | */ |
| 192 | asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); |
| 193 | |
| 194 | /* Invalidate entire branch predictor array */ |
| 195 | asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0)); |
| 196 | |
| 197 | /* Full system DSB - make sure that the invalidation is complete */ |
Tom Rini | 3b787ef | 2016-08-01 18:54:53 -0400 | [diff] [blame] | 198 | dsb(); |
Aneesh V | 960f5c0 | 2011-06-16 23:30:47 +0000 | [diff] [blame] | 199 | |
| 200 | /* ISB - make sure the instruction stream sees it */ |
Tom Rini | 3b787ef | 2016-08-01 18:54:53 -0400 | [diff] [blame] | 201 | isb(); |
Aneesh V | 960f5c0 | 2011-06-16 23:30:47 +0000 | [diff] [blame] | 202 | } |
| 203 | #else |
| 204 | void invalidate_icache_all(void) |
| 205 | { |
| 206 | } |
| 207 | #endif |
| 208 | |
Jeroen Hofstee | d746077 | 2014-06-23 22:07:04 +0200 | [diff] [blame] | 209 | /* Stub implementations for outer cache operations */ |
| 210 | __weak void v7_outer_cache_enable(void) {} |
| 211 | __weak void v7_outer_cache_disable(void) {} |
| 212 | __weak void v7_outer_cache_flush_all(void) {} |
| 213 | __weak void v7_outer_cache_inval_all(void) {} |
| 214 | __weak void v7_outer_cache_flush_range(u32 start, u32 end) {} |
| 215 | __weak void v7_outer_cache_inval_range(u32 start, u32 end) {} |