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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Aneesh V960f5c02011-06-16 23:30:47 +00002/*
3 * (C) Copyright 2010
4 * Texas Instruments, <www.ti.com>
5 * Aneesh V <aneesh@ti.com>
Aneesh V960f5c02011-06-16 23:30:47 +00006 */
Simon Glass63334482019-11-14 12:57:39 -07007#include <cpu_func.h>
Simon Glass274e0b02020-05-10 11:39:56 -06008#include <asm/cache.h>
Aneesh V960f5c02011-06-16 23:30:47 +00009#include <linux/types.h>
10#include <common.h>
11#include <asm/armv7.h>
12#include <asm/utils.h>
13
Hans de Goedeba3bf9b2016-04-09 13:53:49 +020014#define ARMV7_DCACHE_INVAL_RANGE 1
15#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 2
Aneesh V960f5c02011-06-16 23:30:47 +000016
Trevor Woerner43ec7e02019-05-03 09:41:00 -040017#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
Hans de Goede076e8412016-04-09 13:53:48 +020018
19/* Asm functions from cache_v7_asm.S */
20void v7_flush_dcache_all(void);
Hans de Goedeba3bf9b2016-04-09 13:53:49 +020021void v7_invalidate_dcache_all(void);
Hans de Goede076e8412016-04-09 13:53:48 +020022
Aneesh V960f5c02011-06-16 23:30:47 +000023static u32 get_ccsidr(void)
24{
25 u32 ccsidr;
26
27 /* Read current CP15 Cache Size ID Register */
28 asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr));
29 return ccsidr;
30}
31
Thierry Reding0c597382014-08-26 17:34:20 +020032static void v7_dcache_clean_inval_range(u32 start, u32 stop, u32 line_len)
Aneesh V960f5c02011-06-16 23:30:47 +000033{
34 u32 mva;
35
36 /* Align start to cache line boundary */
37 start &= ~(line_len - 1);
38 for (mva = start; mva < stop; mva = mva + line_len) {
39 /* DCCIMVAC - Clean & Invalidate data cache by MVA to PoC */
40 asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva));
41 }
42}
43
44static void v7_dcache_inval_range(u32 start, u32 stop, u32 line_len)
45{
46 u32 mva;
47
Simon Glassb7ba9572016-06-19 19:43:02 -060048 if (!check_cache_range(start, stop))
49 return;
Aneesh V960f5c02011-06-16 23:30:47 +000050
51 for (mva = start; mva < stop; mva = mva + line_len) {
52 /* DCIMVAC - Invalidate data cache by MVA to PoC */
53 asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva));
54 }
55}
56
57static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op)
58{
59 u32 line_len, ccsidr;
60
61 ccsidr = get_ccsidr();
62 line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >>
63 CCSIDR_LINE_SIZE_OFFSET) + 2;
64 /* Converting from words to bytes */
65 line_len += 2;
66 /* converting from log2(linelen) to linelen */
67 line_len = 1 << line_len;
68
69 switch (range_op) {
70 case ARMV7_DCACHE_CLEAN_INVAL_RANGE:
71 v7_dcache_clean_inval_range(start, stop, line_len);
72 break;
73 case ARMV7_DCACHE_INVAL_RANGE:
74 v7_dcache_inval_range(start, stop, line_len);
75 break;
76 }
77
Aneesh V517912b2011-08-11 04:35:44 +000078 /* DSB to make sure the operation is complete */
Tom Rini3b787ef2016-08-01 18:54:53 -040079 dsb();
Aneesh V960f5c02011-06-16 23:30:47 +000080}
81
82/* Invalidate TLB */
83static void v7_inval_tlb(void)
84{
85 /* Invalidate entire unified TLB */
86 asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
87 /* Invalidate entire data TLB */
88 asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0));
89 /* Invalidate entire instruction TLB */
90 asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
91 /* Full system DSB - make sure that the invalidation is complete */
Tom Rini3b787ef2016-08-01 18:54:53 -040092 dsb();
Aneesh V960f5c02011-06-16 23:30:47 +000093 /* Full system ISB - make sure the instruction stream sees it */
Tom Rini3b787ef2016-08-01 18:54:53 -040094 isb();
Aneesh V960f5c02011-06-16 23:30:47 +000095}
96
97void invalidate_dcache_all(void)
98{
Hans de Goedeba3bf9b2016-04-09 13:53:49 +020099 v7_invalidate_dcache_all();
Aneesh V960f5c02011-06-16 23:30:47 +0000100
101 v7_outer_cache_inval_all();
102}
103
104/*
105 * Performs a clean & invalidation of the entire data cache
106 * at all levels
107 */
108void flush_dcache_all(void)
109{
Hans de Goede076e8412016-04-09 13:53:48 +0200110 v7_flush_dcache_all();
Aneesh V960f5c02011-06-16 23:30:47 +0000111
112 v7_outer_cache_flush_all();
113}
114
115/*
116 * Invalidates range in all levels of D-cache/unified cache used:
117 * Affects the range [start, stop - 1]
118 */
119void invalidate_dcache_range(unsigned long start, unsigned long stop)
120{
Marek Vasutc28ad232015-07-27 22:34:17 +0200121 check_cache_range(start, stop);
122
Aneesh V960f5c02011-06-16 23:30:47 +0000123 v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE);
124
125 v7_outer_cache_inval_range(start, stop);
126}
127
128/*
129 * Flush range(clean & invalidate) from all levels of D-cache/unified
130 * cache used:
131 * Affects the range [start, stop - 1]
132 */
133void flush_dcache_range(unsigned long start, unsigned long stop)
134{
Marek Vasutc28ad232015-07-27 22:34:17 +0200135 check_cache_range(start, stop);
136
Aneesh V960f5c02011-06-16 23:30:47 +0000137 v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE);
138
139 v7_outer_cache_flush_range(start, stop);
140}
141
142void arm_init_before_mmu(void)
143{
144 v7_outer_cache_enable();
145 invalidate_dcache_all();
146 v7_inval_tlb();
147}
148
Simon Glassa4f20792012-10-17 13:24:53 +0000149void mmu_page_table_flush(unsigned long start, unsigned long stop)
150{
151 flush_dcache_range(start, stop);
152 v7_inval_tlb();
153}
Trevor Woerner43ec7e02019-05-03 09:41:00 -0400154#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
Aneesh V960f5c02011-06-16 23:30:47 +0000155void invalidate_dcache_all(void)
156{
157}
158
159void flush_dcache_all(void)
160{
161}
162
Daniel Allred4631f7d2016-06-27 09:19:16 -0500163void invalidate_dcache_range(unsigned long start, unsigned long stop)
164{
165}
166
167void flush_dcache_range(unsigned long start, unsigned long stop)
168{
169}
170
Aneesh V960f5c02011-06-16 23:30:47 +0000171void arm_init_before_mmu(void)
172{
173}
174
Simon Glassa4f20792012-10-17 13:24:53 +0000175void mmu_page_table_flush(unsigned long start, unsigned long stop)
176{
177}
178
R Sricharan06396c12013-03-04 20:04:45 +0000179void arm_init_domains(void)
180{
181}
Trevor Woerner43ec7e02019-05-03 09:41:00 -0400182#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
Aneesh V960f5c02011-06-16 23:30:47 +0000183
Trevor Woerner43ec7e02019-05-03 09:41:00 -0400184#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
Aneesh V960f5c02011-06-16 23:30:47 +0000185/* Invalidate entire I-cache and branch predictor array */
186void invalidate_icache_all(void)
187{
188 /*
189 * Invalidate all instruction caches to PoU.
190 * Also flushes branch target cache.
191 */
192 asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
193
194 /* Invalidate entire branch predictor array */
195 asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
196
197 /* Full system DSB - make sure that the invalidation is complete */
Tom Rini3b787ef2016-08-01 18:54:53 -0400198 dsb();
Aneesh V960f5c02011-06-16 23:30:47 +0000199
200 /* ISB - make sure the instruction stream sees it */
Tom Rini3b787ef2016-08-01 18:54:53 -0400201 isb();
Aneesh V960f5c02011-06-16 23:30:47 +0000202}
203#else
204void invalidate_icache_all(void)
205{
206}
207#endif
208
Jeroen Hofsteed7460772014-06-23 22:07:04 +0200209/* Stub implementations for outer cache operations */
210__weak void v7_outer_cache_enable(void) {}
211__weak void v7_outer_cache_disable(void) {}
212__weak void v7_outer_cache_flush_all(void) {}
213__weak void v7_outer_cache_inval_all(void) {}
214__weak void v7_outer_cache_flush_range(u32 start, u32 end) {}
215__weak void v7_outer_cache_inval_range(u32 start, u32 end) {}