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git01.mediatek.com / filogic / uboot / be479a81dce4b64f6046c1c52fb3842e6392ea99 / . / board / samsung / smdkc100 / mem_setup.S
blob: 94a701d428d29158197f794cfc9a4ee0f331182b [file] [log] [blame]
Minkyu Kang29325572009-10-01 17:20:40 +0900[diff] [blame]1/*
2 * Originates from Samsung's u-boot 1.1.6 port to S5PC1xx
3 *
4 * Copyright (C) 2009 Samsung Electrnoics
5 * Inki Dae <inki.dae@samsung.com>
6 * Heungjun Kim <riverful.kim@samsung.com>
7 * Minkyu Kang <mk7.kang@samsung.com>
8 * Kyungmin Park <kyungmin.park@samsung.com>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#include <config.h>
30
31 .globl mem_ctrl_asm_init
32mem_ctrl_asm_init:
33 ldr r6, =S5PC100_DMC_BASE @ 0xE6000000
34
35 /* DLL parameter setting */
36 ldr r1, =0x50101000
37 str r1, [r6, #0x018] @ PHYCONTROL0
38 ldr r1, =0xf4
39 str r1, [r6, #0x01C] @ PHYCONTROL1
40 ldr r1, =0x0
41 str r1, [r6, #0x020] @ PHYCONTROL2
42
43 /* DLL on */
44 ldr r1, =0x50101002
45 str r1, [r6, #0x018] @ PHYCONTROL0
46
47 /* DLL start */
48 ldr r1, =0x50101003
49 str r1, [r6, #0x018] @ PHYCONTROL0
50
51 /* Force value locking for DLL off */
52 str r1, [r6, #0x018] @ PHYCONTROL0
53
54 /* DLL off */
55 ldr r1, =0x50101001
56 str r1, [r6, #0x018] @ PHYCONTROL0
57
58 /* auto refresh off */
59 ldr r1, =0xff001010
60 str r1, [r6, #0x000] @ CONCONTROL
61
62 /*
63 * Burst Length 4, 2 chips, 32-bit, LPDDR
64 * OFF: dynamic self refresh, force precharge, dynamic power down off
65 */
66 ldr r1, =0x00212100
67 str r1, [r6, #0x004] @ MEMCONTROL
68
69 /*
70 * Note:
71 * If Bank0 has OneDRAM we place it at 0x2800'0000
72 * So finally Bank1 should address start at at 0x2000'0000
73 */
74 mov r4, #0x0
75
76swap_memory:
77 /*
78 * Bank0
79 * 0x30 -> 0x30000000
80 * 0xf8 -> 0x37FFFFFF
81 * [15:12] 0: Linear
82 * [11:8 ] 2: 9 bits
83 * [ 7:4 ] 2: 14 bits
84 * [ 3:0 ] 2: 4 banks
85 */
86 ldr r1, =0x30f80222
87 /* if r4 is 1, swap the bank */
88 cmp r4, #0x1
89 orreq r1, r1, #0x08000000
90 str r1, [r6, #0x008] @ MEMCONFIG0
91
92 /*
93 * Bank1
94 * 0x38 -> 0x38000000
95 * 0xf8 -> 0x3fFFFFFF
96 * [15:12] 0: Linear
97 * [11:8 ] 2: 9 bits
98 * [ 7:4 ] 2: 14 bits
99 * [ 3:0 ] 2: 4 banks
100 */
101 ldr r1, =0x38f80222
102 /* if r4 is 1, swap the bank */
103 cmp r4, #0x1
104 biceq r1, r1, #0x08000000
105 str r1, [r6, #0x00c] @ MEMCONFIG1
106
107 ldr r1, =0x20000000
108 str r1, [r6, #0x014] @ PRECHCONFIG
109
110 /*
111 * FIXME: Please verify these values
112 * 7.8us * 166MHz %LE %LONG1294(0x50E)
113 * 7.8us * 133MHz %LE %LONG1038(0x40E),
114 * 7.8us * 100MHz %LE %LONG780(0x30C),
115 * 7.8us * 20MHz %LE %LONG156(0x9C),
116 * 7.8us * 10MHz %LE %LONG78(0x4E)
117 */
118 ldr r1, =0x0000050e
119 str r1, [r6, #0x030] @ TIMINGAREF
120
121 /* 166 MHz */
122 ldr r1, =0x0c233287
123 str r1, [r6, #0x034] @ TIMINGROW
124
125 /* twtr=3 twr=2 trtp=3 cl=3 wl=3 rl=3 */
126 ldr r1, =0x32330303
127 str r1, [r6, #0x038] @ TIMINGDATA
128
129 /* tfaw=4 sxsr=0x14 txp=0x14 tcke=3 tmrd=3 */
130 ldr r1, =0x04141433
131 str r1, [r6, #0x03C] @ TIMINGPOWER
132
133 /* chip0 Deselect */
134 ldr r1, =0x07000000
135 str r1, [r6, #0x010] @ DIRECTCMD
136
137 /* chip0 PALL */
138 ldr r1, =0x01000000
139 str r1, [r6, #0x010] @ DIRECTCMD
140
141 /* chip0 REFA */
142 ldr r1, =0x05000000
143 str r1, [r6, #0x010] @ DIRECTCMD
144 /* chip0 REFA */
145 str r1, [r6, #0x010] @ DIRECTCMD
146
147 /* chip0 MRS, CL%LE %LONG3, BL%LE %LONG4 */
148 ldr r1, =0x00000032
149 str r1, [r6, #0x010] @ DIRECTCMD
150
151 /* chip1 Deselect */
152 ldr r1, =0x07100000
153 str r1, [r6, #0x010] @ DIRECTCMD
154
155 /* chip1 PALL */
156 ldr r1, =0x01100000
157 str r1, [r6, #0x010] @ DIRECTCMD
158
159 /* chip1 REFA */
160 ldr r1, =0x05100000
161 str r1, [r6, #0x010] @ DIRECTCMD
162 /* chip1 REFA */
163 str r1, [r6, #0x010] @ DIRECTCMD
164
165 /* chip1 MRS, CL%LE %LONG3, BL%LE %LONG4 */
166 ldr r1, =0x00100032
167 str r1, [r6, #0x010] @ DIRECTCMD
168
169 /* auto refresh on */
170 ldr r1, =0xff002030
171 str r1, [r6, #0x000] @ CONCONTROL
172
173 /* PwrdnConfig */
174 ldr r1, =0x00100002
175 str r1, [r6, #0x028] @ PWRDNCONFIG
176
177 /* BL%LE %LONG */
178 ldr r1, =0xff212100
179 str r1, [r6, #0x004] @ MEMCONTROL
180
181
182 /* Try to test memory area */
183 cmp r4, #0x1
184 beq 1f
185
186 mov r4, #0x1
187 ldr r1, =0x37ffff00
188 str r4, [r1]
189 str r4, [r1, #0x4] @ dummy write
190 ldr r0, [r1]
191 cmp r0, r4
192 bne swap_memory
193
1941:
195 mov pc, lr
196
197 .ltorg