blob: 1782cffc404aab20f574fcc894eaf23a88e04aaa [file] [log] [blame]
Jagan Teki1d150b42018-12-22 21:32:49 +05301// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
Simon Glass0f2af882020-05-10 11:40:05 -060011#include <log.h>
Andre Przywara030bab82019-01-29 15:54:08 +000012#include <reset.h>
Jagan Teki1d150b42018-12-22 21:32:49 +053013#include <asm/io.h>
Samuel Holland12e3faa2021-09-12 11:48:43 -050014#include <clk/sunxi.h>
Samuel Holland86b561c2022-05-09 00:29:37 -050015#include <dm/device-internal.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060016#include <linux/bitops.h>
Jagan Teki1d150b42018-12-22 21:32:49 +053017#include <linux/log2.h>
18
Samuel Holland86b561c2022-05-09 00:29:37 -050019extern U_BOOT_DRIVER(sunxi_reset);
20
Samuel Holland90315322022-05-09 00:29:35 -050021static const struct ccu_clk_gate *plat_to_gate(struct ccu_plat *plat,
Jagan Teki1d150b42018-12-22 21:32:49 +053022 unsigned long id)
23{
Samuel Holland90315322022-05-09 00:29:35 -050024 if (id >= plat->desc->num_gates)
Samuel Hollanda4969072022-05-09 00:29:32 -050025 return NULL;
26
Samuel Holland90315322022-05-09 00:29:35 -050027 return &plat->desc->gates[id];
Jagan Teki1d150b42018-12-22 21:32:49 +053028}
29
30static int sunxi_set_gate(struct clk *clk, bool on)
31{
Samuel Holland90315322022-05-09 00:29:35 -050032 struct ccu_plat *plat = dev_get_plat(clk->dev);
33 const struct ccu_clk_gate *gate = plat_to_gate(plat, clk->id);
Jagan Teki1d150b42018-12-22 21:32:49 +053034 u32 reg;
35
Samuel Hollanda4969072022-05-09 00:29:32 -050036 if (gate && (gate->flags & CCU_CLK_F_DUMMY_GATE))
Andre Przywara2d1864f2022-05-05 01:25:43 +010037 return 0;
38
Samuel Hollanda4969072022-05-09 00:29:32 -050039 if (!gate || !(gate->flags & CCU_CLK_F_IS_VALID)) {
Jagan Teki1d150b42018-12-22 21:32:49 +053040 printf("%s: (CLK#%ld) unhandled\n", __func__, clk->id);
41 return 0;
42 }
43
44 debug("%s: (CLK#%ld) off#0x%x, BIT(%d)\n", __func__,
45 clk->id, gate->off, ilog2(gate->bit));
46
Samuel Holland90315322022-05-09 00:29:35 -050047 reg = readl(plat->base + gate->off);
Jagan Teki1d150b42018-12-22 21:32:49 +053048 if (on)
49 reg |= gate->bit;
50 else
51 reg &= ~gate->bit;
52
Samuel Holland90315322022-05-09 00:29:35 -050053 writel(reg, plat->base + gate->off);
Jagan Teki1d150b42018-12-22 21:32:49 +053054
55 return 0;
56}
57
58static int sunxi_clk_enable(struct clk *clk)
59{
60 return sunxi_set_gate(clk, true);
61}
62
63static int sunxi_clk_disable(struct clk *clk)
64{
65 return sunxi_set_gate(clk, false);
66}
67
68struct clk_ops sunxi_clk_ops = {
69 .enable = sunxi_clk_enable,
70 .disable = sunxi_clk_disable,
71};
72
Samuel Holland751c6c62022-05-09 00:29:34 -050073static int sunxi_clk_bind(struct udevice *dev)
Samuel Holland1567fdf2022-05-09 00:29:33 -050074{
Samuel Holland86b561c2022-05-09 00:29:37 -050075 /* Reuse the platform data for the reset driver. */
76 return device_bind(dev, DM_DRIVER_REF(sunxi_reset), "reset",
77 dev_get_plat(dev), dev_ofnode(dev), NULL);
Samuel Holland1567fdf2022-05-09 00:29:33 -050078}
79
Samuel Holland751c6c62022-05-09 00:29:34 -050080static int sunxi_clk_probe(struct udevice *dev)
Jagan Teki1d150b42018-12-22 21:32:49 +053081{
Andre Przywara030bab82019-01-29 15:54:08 +000082 struct clk_bulk clk_bulk;
83 struct reset_ctl_bulk rst_bulk;
84 int ret;
Jagan Teki1d150b42018-12-22 21:32:49 +053085
Andre Przywara030bab82019-01-29 15:54:08 +000086 ret = clk_get_bulk(dev, &clk_bulk);
87 if (!ret)
88 clk_enable_bulk(&clk_bulk);
89
90 ret = reset_get_bulk(dev, &rst_bulk);
91 if (!ret)
92 reset_deassert_bulk(&rst_bulk);
93
Jagan Teki1d150b42018-12-22 21:32:49 +053094 return 0;
95}
Samuel Holland751c6c62022-05-09 00:29:34 -050096
Samuel Holland90315322022-05-09 00:29:35 -050097static int sunxi_clk_of_to_plat(struct udevice *dev)
98{
99 struct ccu_plat *plat = dev_get_plat(dev);
100
101 plat->base = dev_read_addr_ptr(dev);
102 if (!plat->base)
103 return -ENOMEM;
104
105 plat->desc = (const struct ccu_desc *)dev_get_driver_data(dev);
106 if (!plat->desc)
107 return -EINVAL;
108
109 return 0;
110}
111
Samuel Holland751c6c62022-05-09 00:29:34 -0500112extern const struct ccu_desc a10_ccu_desc;
113extern const struct ccu_desc a10s_ccu_desc;
114extern const struct ccu_desc a23_ccu_desc;
115extern const struct ccu_desc a31_ccu_desc;
116extern const struct ccu_desc a31_r_ccu_desc;
117extern const struct ccu_desc a64_ccu_desc;
118extern const struct ccu_desc a80_ccu_desc;
119extern const struct ccu_desc a80_mmc_clk_desc;
120extern const struct ccu_desc a83t_ccu_desc;
Samuel Holland934d0f52022-04-30 22:38:37 -0500121extern const struct ccu_desc d1_ccu_desc;
Samuel Holland751c6c62022-05-09 00:29:34 -0500122extern const struct ccu_desc f1c100s_ccu_desc;
123extern const struct ccu_desc h3_ccu_desc;
124extern const struct ccu_desc h6_ccu_desc;
125extern const struct ccu_desc h616_ccu_desc;
126extern const struct ccu_desc h6_r_ccu_desc;
127extern const struct ccu_desc r40_ccu_desc;
128extern const struct ccu_desc v3s_ccu_desc;
129
130static const struct udevice_id sunxi_clk_ids[] = {
131#ifdef CONFIG_CLK_SUN4I_A10
132 { .compatible = "allwinner,sun4i-a10-ccu",
133 .data = (ulong)&a10_ccu_desc },
134#endif
135#ifdef CONFIG_CLK_SUN5I_A10S
136 { .compatible = "allwinner,sun5i-a10s-ccu",
137 .data = (ulong)&a10s_ccu_desc },
138 { .compatible = "allwinner,sun5i-a13-ccu",
139 .data = (ulong)&a10s_ccu_desc },
140#endif
141#ifdef CONFIG_CLK_SUN6I_A31
142 { .compatible = "allwinner,sun6i-a31-ccu",
143 .data = (ulong)&a31_ccu_desc },
144#endif
145#ifdef CONFIG_CLK_SUN4I_A10
146 { .compatible = "allwinner,sun7i-a20-ccu",
147 .data = (ulong)&a10_ccu_desc },
148#endif
149#ifdef CONFIG_CLK_SUN8I_A23
150 { .compatible = "allwinner,sun8i-a23-ccu",
151 .data = (ulong)&a23_ccu_desc },
152 { .compatible = "allwinner,sun8i-a33-ccu",
153 .data = (ulong)&a23_ccu_desc },
154#endif
155#ifdef CONFIG_CLK_SUN8I_A83T
156 { .compatible = "allwinner,sun8i-a83t-ccu",
157 .data = (ulong)&a83t_ccu_desc },
158#endif
159#ifdef CONFIG_CLK_SUN6I_A31_R
160 { .compatible = "allwinner,sun8i-a83t-r-ccu",
161 .data = (ulong)&a31_r_ccu_desc },
162#endif
163#ifdef CONFIG_CLK_SUN8I_H3
164 { .compatible = "allwinner,sun8i-h3-ccu",
165 .data = (ulong)&h3_ccu_desc },
166#endif
167#ifdef CONFIG_CLK_SUN6I_A31_R
168 { .compatible = "allwinner,sun8i-h3-r-ccu",
169 .data = (ulong)&a31_r_ccu_desc },
170#endif
171#ifdef CONFIG_CLK_SUN8I_R40
172 { .compatible = "allwinner,sun8i-r40-ccu",
173 .data = (ulong)&r40_ccu_desc },
174#endif
175#ifdef CONFIG_CLK_SUN8I_V3S
176 { .compatible = "allwinner,sun8i-v3-ccu",
177 .data = (ulong)&v3s_ccu_desc },
178 { .compatible = "allwinner,sun8i-v3s-ccu",
179 .data = (ulong)&v3s_ccu_desc },
180#endif
181#ifdef CONFIG_CLK_SUN9I_A80
182 { .compatible = "allwinner,sun9i-a80-ccu",
183 .data = (ulong)&a80_ccu_desc },
184 { .compatible = "allwinner,sun9i-a80-mmc-config-clk",
185 .data = (ulong)&a80_mmc_clk_desc },
186#endif
187#ifdef CONFIG_CLK_SUN50I_A64
188 { .compatible = "allwinner,sun50i-a64-ccu",
189 .data = (ulong)&a64_ccu_desc },
190#endif
191#ifdef CONFIG_CLK_SUN6I_A31_R
192 { .compatible = "allwinner,sun50i-a64-r-ccu",
193 .data = (ulong)&a31_r_ccu_desc },
194#endif
195#ifdef CONFIG_CLK_SUN8I_H3
196 { .compatible = "allwinner,sun50i-h5-ccu",
197 .data = (ulong)&h3_ccu_desc },
198#endif
Samuel Holland934d0f52022-04-30 22:38:37 -0500199#ifdef CONFIG_CLK_SUN20I_D1
200 { .compatible = "allwinner,sun20i-d1-ccu",
201 .data = (ulong)&d1_ccu_desc },
202#endif
Samuel Holland751c6c62022-05-09 00:29:34 -0500203#ifdef CONFIG_CLK_SUN50I_H6
204 { .compatible = "allwinner,sun50i-h6-ccu",
205 .data = (ulong)&h6_ccu_desc },
206#endif
207#ifdef CONFIG_CLK_SUN50I_H6_R
208 { .compatible = "allwinner,sun50i-h6-r-ccu",
209 .data = (ulong)&h6_r_ccu_desc },
210#endif
211#ifdef CONFIG_CLK_SUN50I_H616
212 { .compatible = "allwinner,sun50i-h616-ccu",
213 .data = (ulong)&h616_ccu_desc },
214#endif
215#ifdef CONFIG_CLK_SUN50I_H6_R
216 { .compatible = "allwinner,sun50i-h616-r-ccu",
217 .data = (ulong)&h6_r_ccu_desc },
218#endif
219#ifdef CONFIG_CLK_SUNIV_F1C100S
220 { .compatible = "allwinner,suniv-f1c100s-ccu",
221 .data = (ulong)&f1c100s_ccu_desc },
222#endif
223 { }
224};
225
226U_BOOT_DRIVER(sunxi_clk) = {
227 .name = "sunxi_clk",
228 .id = UCLASS_CLK,
229 .of_match = sunxi_clk_ids,
230 .bind = sunxi_clk_bind,
231 .probe = sunxi_clk_probe,
Samuel Holland90315322022-05-09 00:29:35 -0500232 .of_to_plat = sunxi_clk_of_to_plat,
233 .plat_auto = sizeof(struct ccu_plat),
Samuel Holland751c6c62022-05-09 00:29:34 -0500234 .ops = &sunxi_clk_ops,
235};