Christophe Leroy | 684a485 | 2017-07-06 10:33:11 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2000 |
| 3 | * Subodh Nijsure, SkyStream Networks, snijsure@skystream.com |
| 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <mpc8xx.h> |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 10 | #include <asm/io.h> |
Christophe Leroy | 31f6e93 | 2017-07-13 15:09:54 +0200 | [diff] [blame] | 11 | #include <asm/ppc.h> |
Christophe Leroy | 684a485 | 2017-07-06 10:33:11 +0200 | [diff] [blame] | 12 | |
Christophe Leroy | 31f6e93 | 2017-07-13 15:09:54 +0200 | [diff] [blame] | 13 | void print_reginfo(void) |
Christophe Leroy | 684a485 | 2017-07-06 10:33:11 +0200 | [diff] [blame] | 14 | { |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 15 | immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; |
| 16 | memctl8xx_t __iomem *memctl = &immap->im_memctl; |
| 17 | sysconf8xx_t __iomem *sysconf = &immap->im_siu_conf; |
| 18 | sit8xx_t __iomem *timers = &immap->im_sit; |
Christophe Leroy | 684a485 | 2017-07-06 10:33:11 +0200 | [diff] [blame] | 19 | |
| 20 | /* Hopefully more PowerPC knowledgable people will add code to display |
| 21 | * other useful registers |
| 22 | */ |
| 23 | |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 24 | printf("\nSystem Configuration registers\n" |
Christophe Leroy | bda8947 | 2018-03-16 17:20:39 +0100 | [diff] [blame^] | 25 | "\tIMMR\t0x%08X\n", get_immr()); |
Christophe Leroy | 684a485 | 2017-07-06 10:33:11 +0200 | [diff] [blame] | 26 | |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 27 | printf("\tSIUMCR\t0x%08X", in_be32(&sysconf->sc_siumcr)); |
| 28 | printf("\tSYPCR\t0x%08X\n", in_be32(&sysconf->sc_sypcr)); |
Christophe Leroy | 684a485 | 2017-07-06 10:33:11 +0200 | [diff] [blame] | 29 | |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 30 | printf("\tSWT\t0x%08X", in_be32(&sysconf->sc_swt)); |
| 31 | printf("\tSWSR\t0x%04X\n", in_be16(&sysconf->sc_swsr)); |
Christophe Leroy | 684a485 | 2017-07-06 10:33:11 +0200 | [diff] [blame] | 32 | |
| 33 | printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n", |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 34 | in_be32(&sysconf->sc_sipend), in_be32(&sysconf->sc_simask)); |
Christophe Leroy | 684a485 | 2017-07-06 10:33:11 +0200 | [diff] [blame] | 35 | printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n", |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 36 | in_be32(&sysconf->sc_siel), in_be32(&sysconf->sc_sivec)); |
Christophe Leroy | 684a485 | 2017-07-06 10:33:11 +0200 | [diff] [blame] | 37 | printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n", |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 38 | in_be32(&sysconf->sc_tesr), in_be32(&sysconf->sc_sdcr)); |
Christophe Leroy | 684a485 | 2017-07-06 10:33:11 +0200 | [diff] [blame] | 39 | |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 40 | printf("Memory Controller Registers\n"); |
| 41 | printf("\tBR0\t0x%08X\tOR0\t0x%08X\n", in_be32(&memctl->memc_br0), |
| 42 | in_be32(&memctl->memc_or0)); |
| 43 | printf("\tBR1\t0x%08X\tOR1\t0x%08X\n", in_be32(&memctl->memc_br1), |
| 44 | in_be32(&memctl->memc_or1)); |
| 45 | printf("\tBR2\t0x%08X\tOR2\t0x%08X\n", in_be32(&memctl->memc_br2), |
| 46 | in_be32(&memctl->memc_or2)); |
| 47 | printf("\tBR3\t0x%08X\tOR3\t0x%08X\n", in_be32(&memctl->memc_br3), |
| 48 | in_be32(&memctl->memc_or3)); |
| 49 | printf("\tBR4\t0x%08X\tOR4\t0x%08X\n", in_be32(&memctl->memc_br4), |
| 50 | in_be32(&memctl->memc_or4)); |
| 51 | printf("\tBR5\t0x%08X\tOR5\t0x%08X\n", in_be32(&memctl->memc_br5), |
| 52 | in_be32(&memctl->memc_or5)); |
| 53 | printf("\tBR6\t0x%08X\tOR6\t0x%08X\n", in_be32(&memctl->memc_br6), |
| 54 | in_be32(&memctl->memc_or6)); |
| 55 | printf("\tBR7\t0x%08X\tOR7\t0x%08X\n", in_be32(&memctl->memc_br7), |
| 56 | in_be32(&memctl->memc_or7)); |
| 57 | printf("\n\tmamr\t0x%08X\tmbmr\t0x%08X\n", in_be32(&memctl->memc_mamr), |
| 58 | in_be32(&memctl->memc_mbmr)); |
| 59 | printf("\tmstat\t0x%04X\tmptpr\t0x%04X\n", in_be16(&memctl->memc_mstat), |
| 60 | in_be16(&memctl->memc_mptpr)); |
| 61 | printf("\tmdr\t0x%08X\n", in_be32(&memctl->memc_mdr)); |
Christophe Leroy | 684a485 | 2017-07-06 10:33:11 +0200 | [diff] [blame] | 62 | |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 63 | printf("\nSystem Integration Timers\n"); |
| 64 | printf("\tTBSCR\t0x%04X\tRTCSC\t0x%04X\n", |
| 65 | in_be16(&timers->sit_tbscr), in_be16(&timers->sit_rtcsc)); |
| 66 | printf("\tPISCR\t0x%04X\n", in_be16(&timers->sit_piscr)); |
Christophe Leroy | 684a485 | 2017-07-06 10:33:11 +0200 | [diff] [blame] | 67 | |
| 68 | /* |
| 69 | * May be some CPM info here? |
| 70 | */ |
| 71 | } |