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git01.mediatek.com / filogic / uboot / bd99ae77f19fbf54b1fb69d40ab8db06f091bd91 / . / include / asm-m68k / immap_5227x.h
blob: 1d1e6f1b071d22ce759333eb2e852ff80ad726de [file] [log] [blame]
TsiChungLiewae831cd2008-01-14 17:46:19 -0600[diff] [blame]1/*
2 * MCF5227x Internal Memory Map
3 *
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __IMMAP_5227X__
27#define __IMMAP_5227X__
28
29/* Module Base Addresses */
30#define MMAP_SCM1 (CFG_MBAR + 0x00000000)
31#define MMAP_XBS (CFG_MBAR + 0x00004000)
32#define MMAP_FBCS (CFG_MBAR + 0x00008000)
33#define MMAP_CAN (CFG_MBAR + 0x00020000)
34#define MMAP_RTC (CFG_MBAR + 0x0003C000)
35#define MMAP_SCM2 (CFG_MBAR + 0x00040010)
36#define MMAP_SCM3 (CFG_MBAR + 0x00040070)
37#define MMAP_EDMA (CFG_MBAR + 0x00044000)
38#define MMAP_INTC0 (CFG_MBAR + 0x00048000)
39#define MMAP_INTC1 (CFG_MBAR + 0x0004C000)
40#define MMAP_IACK (CFG_MBAR + 0x00054000)
41#define MMAP_I2C (CFG_MBAR + 0x00058000)
42#define MMAP_DSPI (CFG_MBAR + 0x0005C000)
43#define MMAP_UART0 (CFG_MBAR + 0x00060000)
44#define MMAP_UART1 (CFG_MBAR + 0x00064000)
45#define MMAP_UART2 (CFG_MBAR + 0x00068000)
46#define MMAP_DTMR0 (CFG_MBAR + 0x00070000)
47#define MMAP_DTMR1 (CFG_MBAR + 0x00074000)
48#define MMAP_DTMR2 (CFG_MBAR + 0x00078000)
49#define MMAP_DTMR3 (CFG_MBAR + 0x0007C000)
50#define MMAP_PIT0 (CFG_MBAR + 0x00080000)
51#define MMAP_PIT1 (CFG_MBAR + 0x00084000)
52#define MMAP_PWM (CFG_MBAR + 0x00090000)
53#define MMAP_EPORT (CFG_MBAR + 0x00094000)
54#define MMAP_RCM (CFG_MBAR + 0x000A0000)
55#define MMAP_CCM (CFG_MBAR + 0x000A0004)
56#define MMAP_GPIO (CFG_MBAR + 0x000A4000)
57#define MMAP_ADC (CFG_MBAR + 0x000A8000)
58#define MMAP_LCD (CFG_MBAR + 0x000AC000)
59#define MMAP_LCD_BGLUT (CFG_MBAR + 0x000AC800)
60#define MMAP_LCD_GWLUT (CFG_MBAR + 0x000ACC00)
61#define MMAP_USBHW (CFG_MBAR + 0x000B0000)
62#define MMAP_USBCAPS (CFG_MBAR + 0x000B0100)
63#define MMAP_USBEHCI (CFG_MBAR + 0x000B0140)
64#define MMAP_USBOTG (CFG_MBAR + 0x000B01A0)
65#define MMAP_SDRAM (CFG_MBAR + 0x000B8000)
66#define MMAP_SSI (CFG_MBAR + 0x000BC000)
67#define MMAP_PLL (CFG_MBAR + 0x000C0000)
68
69#include <asm/coldfire/crossbar.h>
70#include <asm/coldfire/dspi.h>
71#include <asm/coldfire/edma.h>
72#include <asm/coldfire/flexbus.h>
73#include <asm/coldfire/lcd.h>
74#include <asm/coldfire/ssi.h>
75
76/* Interrupt Controller (INTC) */
77typedef struct int0_ctrl {
78 u32 iprh0; /* 0x00 Pending Register High */
79 u32 iprl0; /* 0x04 Pending Register Low */
80 u32 imrh0; /* 0x08 Mask Register High */
81 u32 imrl0; /* 0x0C Mask Register Low */
82 u32 frch0; /* 0x10 Force Register High */
83 u32 frcl0; /* 0x14 Force Register Low */
84 u16 res1; /* 0x18 - 0x19 */
85 u16 icfg0; /* 0x1A Configuration Register */
86 u8 simr0; /* 0x1C Set Interrupt Mask */
87 u8 cimr0; /* 0x1D Clear Interrupt Mask */
88 u8 clmask0; /* 0x1E Current Level Mask */
89 u8 slmask; /* 0x1F Saved Level Mask */
90 u32 res2[8]; /* 0x20 - 0x3F */
91 u8 icr0[64]; /* 0x40 - 0x7F Control registers */
92 u32 res3[24]; /* 0x80 - 0xDF */
93 u8 swiack0; /* 0xE0 Software Interrupt ack */
94 u8 res4[3]; /* 0xE1 - 0xE3 */
95 u8 Lniack0_1; /* 0xE4 Level n interrupt ack */
96 u8 res5[3]; /* 0xE5 - 0xE7 */
97 u8 Lniack0_2; /* 0xE8 Level n interrupt ack */
98 u8 res6[3]; /* 0xE9 - 0xEB */
99 u8 Lniack0_3; /* 0xEC Level n interrupt ack */
100 u8 res7[3]; /* 0xED - 0xEF */
101 u8 Lniack0_4; /* 0xF0 Level n interrupt ack */
102 u8 res8[3]; /* 0xF1 - 0xF3 */
103 u8 Lniack0_5; /* 0xF4 Level n interrupt ack */
104 u8 res9[3]; /* 0xF5 - 0xF7 */
105 u8 Lniack0_6; /* 0xF8 Level n interrupt ack */
106 u8 resa[3]; /* 0xF9 - 0xFB */
107 u8 Lniack0_7; /* 0xFC Level n interrupt ack */
108 u8 resb[3]; /* 0xFD - 0xFF */
109} int0_t;
110
111typedef struct int1_ctrl {
112 /* Interrupt Controller 1 */
113 u32 iprh1; /* 0x00 Pending Register High */
114 u32 iprl1; /* 0x04 Pending Register Low */
115 u32 imrh1; /* 0x08 Mask Register High */
116 u32 imrl1; /* 0x0C Mask Register Low */
117 u32 frch1; /* 0x10 Force Register High */
118 u32 frcl1; /* 0x14 Force Register Low */
119 u16 res1; /* 0x18 */
120 u16 icfg1; /* 0x1A Configuration Register */
121 u8 simr1; /* 0x1C Set Interrupt Mask */
122 u8 cimr1; /* 0x1D Clear Interrupt Mask */
123 u16 res2; /* 0x1E - 0x1F */
124 u32 res3[8]; /* 0x20 - 0x3F */
125 u8 icr1[64]; /* 0x40 - 0x7F */
126 u32 res4[24]; /* 0x80 - 0xDF */
127 u8 swiack1; /* 0xE0 Software Interrupt ack */
128 u8 res5[3]; /* 0xE1 - 0xE3 */
129 u8 Lniack1_1; /* 0xE4 Level n interrupt ack */
130 u8 res6[3]; /* 0xE5 - 0xE7 */
131 u8 Lniack1_2; /* 0xE8 Level n interrupt ack */
132 u8 res7[3]; /* 0xE9 - 0xEB */
133 u8 Lniack1_3; /* 0xEC Level n interrupt ack */
134 u8 res8[3]; /* 0xED - 0xEF */
135 u8 Lniack1_4; /* 0xF0 Level n interrupt ack */
136 u8 res9[3]; /* 0xF1 - 0xF3 */
137 u8 Lniack1_5; /* 0xF4 Level n interrupt ack */
138 u8 resa[3]; /* 0xF5 - 0xF7 */
139 u8 Lniack1_6; /* 0xF8 Level n interrupt ack */
140 u8 resb[3]; /* 0xF9 - 0xFB */
141 u8 Lniack1_7; /* 0xFC Level n interrupt ack */
142 u8 resc[3]; /* 0xFD - 0xFF */
143} int1_t;
144
145/* Global Interrupt Acknowledge (IACK) */
146typedef struct iack {
147 u8 resv0[0xE0];
148 u8 gswiack;
149 u8 resv1[0x3];
150 u8 gl1iack;
151 u8 resv2[0x3];
152 u8 gl2iack;
153 u8 resv3[0x3];
154 u8 gl3iack;
155 u8 resv4[0x3];
156 u8 gl4iack;
157 u8 resv5[0x3];
158 u8 gl5iack;
159 u8 resv6[0x3];
160 u8 gl6iack;
161 u8 resv7[0x3];
162 u8 gl7iack;
163} iack_t;
164
165/* Edge Port Module (EPORT) */
166typedef struct eport {
167 u16 eppar;
168 u8 epddr;
169 u8 epier;
170 u8 epdr;
171 u8 eppdr;
172 u8 epfr;
173} eport_t;
174
175/* Reset Controller Module (RCM) */
176typedef struct rcm {
177 u8 rcr;
178 u8 rsr;
179} rcm_t;
180
181/* Chip Configuration Module (CCM) */
182typedef struct ccm {
183 u16 ccr; /* Chip Configuration (Rd-only) */
184 u16 resv1;
185 u16 rcon; /* Reset Configuration (Rd-only) */
186 u16 cir; /* Chip Identification (Rd-only) */
187 u32 resv2;
188 u16 misccr; /* Miscellaneous Control */
189 u16 cdr; /* Clock Divider */
190 u16 uocsr; /* USB On-the-Go Controller Status */
191 u16 resv4;
192 u16 sbfsr; /* Serial Boot Status */
193 u16 sbfcr; /* Serial Boot Control */
194} ccm_t;
195
196/* General Purpose I/O Module (GPIO) */
197typedef struct gpio {
198 /* Port Output Data Registers */
199 u8 podr_be; /* 0x00 */
200 u8 podr_cs; /* 0x01 */
201 u8 podr_fbctl; /* 0x02 */
202 u8 podr_i2c; /* 0x03 */
203 u8 rsvd1; /* 0x04 */
204 u8 podr_uart; /* 0x05 */
205 u8 podr_dspi; /* 0x06 */
206 u8 podr_timer; /* 0x07 */
207 u8 podr_lcdctl; /* 0x08 */
208 u8 podr_lcddatah; /* 0x09 */
209 u8 podr_lcddatam; /* 0x0A */
210 u8 podr_lcddatal; /* 0x0B */
211
212 /* Port Data Direction Registers */
213 u8 pddr_be; /* 0x0C */
214 u8 pddr_cs; /* 0x0D */
215 u8 pddr_fbctl; /* 0x0E */
216 u8 pddr_i2c; /* 0x0F */
217 u8 rsvd2; /* 0x10 */
218 u8 pddr_uart; /* 0x11 */
219 u8 pddr_dspi; /* 0x12 */
220 u8 pddr_timer; /* 0x13 */
221 u8 pddr_lcdctl; /* 0x14 */
222 u8 pddr_lcddatah; /* 0x15 */
223 u8 pddr_lcddatam; /* 0x16 */
224 u8 pddr_lcddatal; /* 0x17 */
225
226 /* Port Pin Data/Set Data Registers */
227 u8 ppdsdr_be; /* 0x18 */
228 u8 ppdsdr_cs; /* 0x19 */
229 u8 ppdsdr_fbctl; /* 0x1A */
230 u8 ppdsdr_i2c; /* 0x1B */
231 u8 rsvd3; /* 0x1C */
232 u8 ppdsdr_uart; /* 0x1D */
233 u8 ppdsdr_dspi; /* 0x1E */
234 u8 ppdsdr_timer; /* 0x1F */
235 u8 ppdsdr_lcdctl; /* 0x20 */
236 u8 ppdsdr_lcddatah; /* 0x21 */
237 u8 ppdsdr_lcddatam; /* 0x22 */
238 u8 ppdsdr_lcddatal; /* 0x23 */
239
240 /* Port Clear Output Data Registers */
241 u8 pclrr_be; /* 0x24 */
242 u8 pclrr_cs; /* 0x25 */
243 u8 pclrr_fbctl; /* 0x26 */
244 u8 pclrr_i2c; /* 0x27 */
245 u8 rsvd4; /* 0x28 */
246 u8 pclrr_uart; /* 0x29 */
247 u8 pclrr_dspi; /* 0x2A */
248 u8 pclrr_timer; /* 0x2B */
249 u8 pclrr_lcdctl; /* 0x2C */
250 u8 pclrr_lcddatah; /* 0x2D */
251 u8 pclrr_lcddatam; /* 0x2E */
252 u8 pclrr_lcddatal; /* 0x2F */
253
254 /* Pin Assignment Registers */
255 u8 par_be; /* 0x30 */
256 u8 par_cs; /* 0x31 */
257 u8 par_fbctl; /* 0x32 */
258 u8 par_i2c; /* 0x33 */
259 u16 par_uart; /* 0x34 */
260 u8 par_dspi; /* 0x36 */
261 u8 par_timer; /* 0x37 */
262 u8 par_lcdctl; /* 0x38 */
263 u8 par_irq; /* 0x39 */
264 u16 rsvd6; /* 0x3A - 0x3B */
265 u32 par_lcdh; /* 0x3C */
266 u32 par_lcdl; /* 0x40 */
267
268 /* Mode select control registers */
269 u8 mscr_fb; /* 0x44 */
270 u8 mscr_sdram; /* 0x45 */
271
272 u16 rsvd7; /* 0x46 - 0x47 */
273 u8 dscr_dspi; /* 0x48 */
274 u8 dscr_timer; /* 0x49 */
275 u8 dscr_i2c; /* 0x4A */
276 u8 dscr_lcd; /* 0x4B */
277 u8 dscr_debug; /* 0x4C */
278 u8 dscr_clkrst; /* 0x4D */
279 u8 dscr_irq; /* 0x4E */
280 u8 dscr_uart; /* 0x4F */
281} gpio_t;
282
283/* SDRAM Controller (SDRAMC) */
284typedef struct sdramc {
285 u32 sdmr; /* Mode/Extended Mode */
286 u32 sdcr; /* Control */
287 u32 sdcfg1; /* Configuration 1 */
288 u32 sdcfg2; /* Chip Select */
289 u8 resv0[0x100];
290 u32 sdcs0; /* Mode/Extended Mode */
291 u32 sdcs1; /* Mode/Extended Mode */
292} sdramc_t;
293
294/* Phase Locked Loop (PLL) */
295typedef struct pll {
296 u32 pcr; /* PLL Control */
297 u32 psr; /* PLL Status */
298} pll_t;
299
300/* System Control Module register */
301typedef struct scm1 {
302 u32 mpr; /* 0x00 Master Privilege */
303 u32 rsvd1[7];
304 u32 pacra; /* 0x20 */
305 u32 pacrb; /* 0x24 */
306 u32 pacrc; /* 0x28 */
307 u32 pacrd; /* 0x2C */
308 u32 rsvd2[4];
309 u32 pacre; /* 0x40 */
310 u32 pacrf; /* 0x44 */
311 u32 pacrg; /* 0x48 */
312 u32 rsvd3;
313 u32 pacri; /* 0x50 */
314} scm1_t;
315
316typedef struct scm2_ctrl {
317 u8 res1[3]; /* 0x00 - 0x02 */
318 u8 wcr; /* 0x03 wakeup control */
319 u16 res2; /* 0x04 - 0x05 */
320 u16 cwcr; /* 0x06 Core Watchdog Control */
321 u8 res3[3]; /* 0x08 - 0x0A */
322 u8 cwsr; /* 0x0B Core Watchdog Service */
323 u8 res4[2]; /* 0x0C - 0x0D */
324 u8 scmisr; /* 0x0F Interrupt Status */
325 u32 res5; /* 0x20 */
326 u32 bcr; /* 0x24 Burst Configuration */
327} scm2_t;
328
329typedef struct scm3_ctrl {
330 u32 cfadr; /* 0x00 Core Fault Address */
331 u8 res7; /* 0x04 */
332 u8 cfier; /* 0x05 Core Fault Interrupt Enable */
333 u8 cfloc; /* 0x06 Core Fault Location */
334 u8 cfatr; /* 0x07 Core Fault Attributes */
335 u32 cfdtr; /* 0x08 Core Fault Data */
336} scm3_t;
337
338typedef struct rtcex {
339 u32 rsvd1[3];
340 u32 gocu;
341 u32 gocl;
342} rtcex_t;
343#endif /* __IMMAP_5227X__ */