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git01.mediatek.com / filogic / uboot / bd905c30170c67618a51af79f9d967a626c7bfc9 / . / arch / mips / mach-ath79 / qca956x / qca956x-ddr-tap.S
blob: db54b575fbc915d6166ef7ef60ef8764f10ea85d [file] [log] [blame]
Rosy Songbd905c32019-03-16 09:24:44 +0800[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019 Rosy Song <rosysong@rosinson.com>
4 *
5 * Based on QSDK
6 */
7
8#include <config.h>
9#include <asm/asm.h>
10#include <asm/regdef.h>
11#include <asm/mipsregs.h>
12#include <asm/addrspace.h>
13#include <mach/ar71xx_regs.h>
14
15 .set noreorder
16
17LEAF(ddr_tap_tuning)
18 li a0, 0xbd001f00
19 sw zero, 0x0(a0) /* Place where the tap values are saved and used for SWEEP */
20 sw zero, 0x4(a0) /* Place where the number of passing taps are saved. */
21 sw zero, 0x14(a0) /* Place where the last pass tap value is stored */
22 li a1, 0xaa55aa55 /* Indicates that the First pass tap value is not found */
23 sw a1, 0x10(a0) /* Place where the First pass tap value is stored */
24 nop
25
26 li a0, CKSEG1ADDR(AR71XX_RESET_BASE) /* RESET_BASE_ADDRESS */
27 lw a1, 0x1c(a0) /* Reading the RST_RESET_ADDRESS */
28 li a2, 0x08000000 /* Setting the RST_RESET_RTC_RESET */
29 or a1, a1, a2
30 sw a1, 0x1c(a0)
31
32 li a3, 0xffffffff
33 xor a2, a2, a3
34 and a1, a1, a2
35 sw a1, 0x1c(a0) /* Taking the RTC out of RESET */
36 nop
37
38 li a0, CKSEG1ADDR(QCA956X_RTC_BASE) /* RTC_BASE_ADDRESS */
39 li a1, 0x1
40 sw a1, 0x0040(a0) /* RTC_SYNC_RESET_ADDRESS */
41
42 li a2, 0x2
43
44_poll_for_RTC_ON:
45 lw a1, 0x0044(a0) /* RTC_SYNC_STATUS_ADDRESS */
46 and a1, a2, a1
47 bne a1, a2, _poll_for_RTC_ON
48 nop
49
50_CHANGE_TAPS:
51 li t0, 0xbd001f00 /* Read the current value of the TAP for programming */
52 lw t1, 0x0(t0)
53 li t2, 0x00000000
54 or t3, t1, t2
55
56 li t0, 0xb8000000 /* DDR_BASE_ADDRESS */
57 sw t3, 0x1c(t0) /* TAP_CONTROL_0_ADDRESS */
58 sw t3, 0x20(t0) /* TAP_CONTROL_1_ADDRESS */
59 sw t3, 0x24(t0) /* TAP_CONTROL_2_ADDRESS */
60 sw t3, 0x28(t0) /* TAP_CONTROL_3_ADDRESS */
61
62 li t1, 0x00000010 /* Running the test 8 times */
63 sw t1, 0x0068(t0) /* PERF_COMP_ADDR_1_ADDRESS */
64
65 li t1, 0xfa5de83f /* 4 Row Address Bits, 4 Column Address Bits, 2 BA bits */
66 sw t1, 0x002c(t0) /* PERF_MASK_ADDR_0_ADDRESS */
67
68 li t1, 0x0000ffff
69 sw t1, 0x0070(t0) /* PERF_COMP_AHB_GE0_1_ADDRESS */
70
71 li t1, 0x0000ffff
72 sw t1, 0x0040(t0) /* PERF_COMP_AHB_GE1_0_ADDRESS */
73
74 li t1, 0x0000ffff
75 sw t1, 0x0078(t0) /* PERF_COMP_AHB_GE1_1_ADDRESS */
76
77 li t1, 0x0000ffff
78 sw t1, 0x0034(t0) /* PERF_MASK_AHB_GE0_0_ADDRESS */
79
80 li t1, 0x0000ffff
81 sw t1, 0x006c(t0) /* PERF_MASK_AHB_GE0_1_ADDRESS */
82
83 li t1, 0x0000ffff
84 sw t1, 0x003c(t0) /* PERF_MASK_AHB_GE1_0_ADDRESS */
85
86 li t1, 0x0000ffff
87 sw t1, 0x0074(t0) /* PERF_MASK_AHB_GE1_1_ADDRESS */
88
89 li t1, 0x0000ffff
90 sw t1, 0x0038(t0) /* PERF_COMP_AHB_GE0_0_ADDRESS */
91
92 li t1, 0x00000001
93 sw t1, 0x011c(t0) /* DDR_BIST_ADDRESS */
94
95 li t2, 0x1
96
97_bist_done_poll:
98 lw t1, 0x0120(t0) /* DDR_BIST_STATUS_ADDRESS */
99 and t1, t1, t2
100 bne t1, t2, _bist_done_poll
101 nop
102
103 lw t1, 0x0120(t0) /* DDR_BIST_STATUS_ADDRESS */
104 li t4, 0x000001fe
105 and t2, t1, t4
106 srl t2, t2, 0x1 /* no. of Pass Runs */
107
108 li t5, 0x00000000
109 sw t5, 0x011c(t0) /* DDR_BIST_ADDRESS - Stop the DDR BIST test */
110
111 li t5, 0x0001fe00
112 and t5, t5, t1
113 bnez t5, _iterate_tap /* This is a redundant compare but nevertheless - Comparing the FAILS */
114 nop
115
116 lw t1, 0x0068(t0) /* PERF_COMP_ADDR_1_ADDRESS */
117 li t3, 0x000001fe
118 and t3, t3, t1
119 srl t3, t3, 0x1 /* No. of runs in the config register. */
120 bne t3, t2, _iterate_tap
121 nop
122
123pass_tap:
124 li t0, 0xbd001f00
125 lw t1, 0x4(t0)
126 addiu t1, t1, 0x1
127 sw t1, 0x4(t0)
128
129 li t0, 0xbd001f10
130 lw t1, 0x0(t0)
131 li t2, 0xaa55aa55
132 beq t1, t2, _first_pass
133 nop
134
135 li t0, 0xbd001f00
136 lw t1, 0x0(t0)
137 li t0, 0xbd001f10
138 sw t1, 0x4(t0)
139 nop
140 b _iterate_tap
141 nop
142
143_first_pass:
144 li t0, 0xbd001f00
145 lw t1, 0x0(t0)
146 li t0, 0xbd001f10
147 sw t1, 0x0(t0)
148 sw t1, 0x4(t0)
149 nop
150
151_iterate_tap:
152 li t0, 0xbd001f00
153 lw t1, 0x0(t0)
154 li t2, 0x3f
155 beq t1, t2, _STOP_TEST
156 nop
157
158 addiu t1, t1, 0x1
159 sw t1, 0x0(t0)
160 nop
161 b _CHANGE_TAPS
162 nop
163
164_STOP_TEST:
165 li t0, 0xbd001f00
166 lw t1, 0x4(t0)
167 bnez t1, _load_center_tap
168 nop
169
170 li t3, 0x8 /* Default Tap to be used */
171 b _load_tap_into_reg
172 nop
173
174_load_center_tap:
175 li t0, 0xbd001f10
176 lw t1, 0x0(t0)
177 lw t2, 0x4(t0)
178 add t3, t1, t2
179 srl t3, t3, 0x1
180 li t4, 0x3f
181 and t3, t3, t4
182
183_load_tap_into_reg:
184 li t0, 0xb8000000
185 sw t3, 0x1c(t0) /* TAP_CONTROL_0_ADDRESS */
186 sw t3, 0x20(t0) /* TAP_CONTROL_1_ADDRESS */
187 sw t3, 0x24(t0) /* TAP_CONTROL_2_ADDRESS */
188 sw t3, 0x28(t0) /* TAP_CONTROL_3_ADDRESS */
189
190 nop
191 jr ra
192 nop
193 END(ddr_tap_tuning)