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git01.mediatek.com / filogic / uboot / bd8ec7e15498ff9dc1043d244fdfaf3bf8c1c02a / . / include / configs / uc101.h
blob: f93dea7b374f49c204f1f6a225e611c774375f9d [file] [log] [blame]
Heiko Schocheracb4f4a2006-12-21 16:14:48 +0100[diff] [blame]1/*
Heiko Schocher028c79f2009-09-23 07:56:04 +0200[diff] [blame]2 * (C) Copyright 2003-2009
Heiko Schocheracb4f4a2006-12-21 16:14:48 +0100[diff] [blame]3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +0200[diff] [blame^]5 * SPDX-License-Identifier: GPL-2.0+
Heiko Schocheracb4f4a2006-12-21 16:14:48 +0100[diff] [blame]6 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11/*
12 * High Level Configuration Options
13 * (easy to change)
14 */
15
Heiko Schocher028c79f2009-09-23 07:56:04 +0200[diff] [blame]16#define CONFIG_UC101 1 /* UC101 board */
17#define CONFIG_HOSTNAME uc101
Heiko Schocheracb4f4a2006-12-21 16:14:48 +0100[diff] [blame]18
Wolfgang Denk291ba1b2010-10-06 09:05:45 +0200[diff] [blame]19#ifndef CONFIG_SYS_TEXT_BASE
20#define CONFIG_SYS_TEXT_BASE 0xFFF00000
21#endif
Wolfgang Denk341e5e72010-11-28 21:18:58 +0100[diff] [blame]22#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds"
Wolfgang Denk291ba1b2010-10-06 09:05:45 +0200[diff] [blame]23
Heiko Schocher028c79f2009-09-23 07:56:04 +0200[diff] [blame]24#include "manroland/common.h"
25#include "manroland/mpc5200-common.h"
Becky Bruce03ea1be2008-05-08 19:02:12 -0500[diff] [blame]26
Heiko Schocheracb4f4a2006-12-21 16:14:48 +0100[diff] [blame]27/*
28 * Serial console configuration
29 */
Heiko Schocheracb4f4a2006-12-21 16:14:48 +0100[diff] [blame]30#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Jon Loeligerc2b1cf02007-07-04 22:33:38 -0500[diff] [blame]31
Heiko Schocheracb4f4a2006-12-21 16:14:48 +0100[diff] [blame]32/*
Jon Loeliger5c4ddae2007-07-10 10:12:10 -0500[diff] [blame]33 * BOOTP options
34 */
35#define CONFIG_BOOTP_BOOTFILESIZE
36#define CONFIG_BOOTP_BOOTPATH
37#define CONFIG_BOOTP_GATEWAY
38#define CONFIG_BOOTP_HOSTNAME
39
Heiko Schocheracb4f4a2006-12-21 16:14:48 +0100[diff] [blame]40/*
Heiko Schocheracb4f4a2006-12-21 16:14:48 +0100[diff] [blame]41 * Flash configuration
42 */
Heiko Schocher028c79f2009-09-23 07:56:04 +0200[diff] [blame]43#define CONFIG_SYS_MAX_FLASH_SECT 140
Heiko Schocheracb4f4a2006-12-21 16:14:48 +0100[diff] [blame]44
45/*
46 * Environment settings
47 */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200[diff] [blame]48#define CONFIG_ENV_SECT_SIZE 0x10000
Heiko Schocheracb4f4a2006-12-21 16:14:48 +0100[diff] [blame]49
50/*
51 * Memory map
52 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]53#define CONFIG_SYS_IB_MASTER 0xc0510000 /* CS 6 */
54#define CONFIG_SYS_IB_EPLD 0xc0500000 /* CS 7 */
Heiko Schocheracb4f4a2006-12-21 16:14:48 +0100[diff] [blame]55
Heiko Schocheracb4f4a2006-12-21 16:14:48 +0100[diff] [blame]56/* SRAM */
Heiko Schocherab8e7f32010-09-13 12:12:33 +0200[diff] [blame]57#define CONFIG_SYS_SRAM_SIZE 0x200000
Heiko Schocheracb4f4a2006-12-21 16:14:48 +0100[diff] [blame]58
Heiko Schocheracb4f4a2006-12-21 16:14:48 +0100[diff] [blame]59/*
Heiko Schocheracb4f4a2006-12-21 16:14:48 +0100[diff] [blame]60 * GPIO configuration
61 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]62#define CONFIG_SYS_GPS_PORT_CONFIG 0x4d558044
Heiko Schocheracb4f4a2006-12-21 16:14:48 +0100[diff] [blame]63
Heiko Schocher028c79f2009-09-23 07:56:04 +0200[diff] [blame]64#define CONFIG_SYS_MEMTEST_START 0x00300000
65#define CONFIG_SYS_MEMTEST_END 0x00f00000
Heiko Schocheracb4f4a2006-12-21 16:14:48 +0100[diff] [blame]66
Heiko Schocher028c79f2009-09-23 07:56:04 +0200[diff] [blame]67#define CONFIG_SYS_LOAD_ADDR 0x300000
Heiko Schocheracb4f4a2006-12-21 16:14:48 +0100[diff] [blame]68
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]69#define CONFIG_SYS_BOOTCS_CFG 0x00045D00
Heiko Schocheracb4f4a2006-12-21 16:14:48 +0100[diff] [blame]70
71/* 8Mbit SRAM @0x80100000 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]72#define CONFIG_SYS_CS1_SIZE 0x00200000
73#define CONFIG_SYS_CS1_CFG 0x21D00
Heiko Schocheracb4f4a2006-12-21 16:14:48 +0100[diff] [blame]74
75/* Display H1, Status Inputs, EPLD @0x80600000 8 Bit */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]76#define CONFIG_SYS_CS3_START CONFIG_SYS_DISPLAY_BASE
77#define CONFIG_SYS_CS3_SIZE 0x00000100
78#define CONFIG_SYS_CS3_CFG 0x00081802
Heiko Schocheracb4f4a2006-12-21 16:14:48 +0100[diff] [blame]79
80/* Interbus Master 16 Bit */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]81#define CONFIG_SYS_CS6_START CONFIG_SYS_IB_MASTER
82#define CONFIG_SYS_CS6_SIZE 0x00010000
83#define CONFIG_SYS_CS6_CFG 0x00FF3500
Heiko Schocheracb4f4a2006-12-21 16:14:48 +0100[diff] [blame]84
85/* Interbus EPLD 8 Bit */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]86#define CONFIG_SYS_CS7_START CONFIG_SYS_IB_EPLD
87#define CONFIG_SYS_CS7_SIZE 0x00010000
88#define CONFIG_SYS_CS7_CFG 0x00081800
Heiko Schocheracb4f4a2006-12-21 16:14:48 +0100[diff] [blame]89
Heiko Schocheracb4f4a2006-12-21 16:14:48 +0100[diff] [blame]90/*-----------------------------------------------------------------------
91 * IDE/ATA stuff Supports IDE harddisk
92 *-----------------------------------------------------------------------
93 */
94
Heiko Schocher028c79f2009-09-23 07:56:04 +0200[diff] [blame]95#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus*/
Heiko Schocheracb4f4a2006-12-21 16:14:48 +0100[diff] [blame]96
97/*---------------------------------------------------------------------*/
98/* Display addresses */
99/*---------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]100#define CONFIG_SYS_DISP_CHR_RAM (CONFIG_SYS_DISPLAY_BASE + 0x38)
101#define CONFIG_SYS_DISP_CWORD (CONFIG_SYS_DISPLAY_BASE + 0x30)
Heiko Schocheracb4f4a2006-12-21 16:14:48 +0100[diff] [blame]102
103#endif /* __CONFIG_H */