| wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 3 | * SPDX-License-Identifier: GPL-2.0+ |
| wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <ppc_asm.tmpl> |
| 7 | #include <config.h> |
| Peter Tyser | 133c0fe | 2010-04-12 22:28:07 -0500 | [diff] [blame] | 8 | #include <asm/mmu.h> |
| Stefan Roese | 3ddce57 | 2010-09-20 16:05:31 +0200 | [diff] [blame] | 9 | #include <asm/ppc4xx.h> |
| wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 10 | |
| 11 | /************************************************************************** |
| 12 | * TLB TABLE |
| 13 | * |
| 14 | * This table is used by the cpu boot code to setup the initial tlb |
| 15 | * entries. Rather than make broad assumptions in the cpu source tree, |
| 16 | * this table lets each board set things up however they like. |
| 17 | * |
| 18 | * Pointer to the table is returned in r1 |
| 19 | * |
| 20 | *************************************************************************/ |
| 21 | |
| Stefan Roese | 76e5308 | 2007-03-16 21:11:42 +0100 | [diff] [blame] | 22 | .section .bootpg,"ax" |
| 23 | .globl tlbtab |
| wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 24 | |
| 25 | tlbtab: |
| Stefan Roese | 76e5308 | 2007-03-16 21:11:42 +0100 | [diff] [blame] | 26 | tlbtab_start |
| 27 | |
| Stefan Roese | 94b6270 | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 28 | tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG) |
| Stefan Roese | 76e5308 | 2007-03-16 21:11:42 +0100 | [diff] [blame] | 29 | |
| 30 | /* |
| 31 | * TLB entries for SDRAM are not needed on this platform. |
| 32 | * They are dynamically generated in the SPD DDR(2) detection |
| 33 | * routine. |
| 34 | */ |
| 35 | |
| Stefan Roese | 94b6270 | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 36 | tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG) |
| 37 | tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX) |
| 38 | tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX) |
| 39 | tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG) |
| 40 | tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG) |
| Stefan Roese | 76e5308 | 2007-03-16 21:11:42 +0100 | [diff] [blame] | 41 | tlbtab_end |