Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / bd4beeb2f2e4b0e62a9d52b6d8347ed931ec15ea / . / arch / arm / dts / imx8mn-bsh-smm-s2-common.dtsi
blob: 184c715bd3821e1365189bcdc5c3ffa9a4f30288 [file] [log] [blame]
Ariel D'Alessandro93add532022-04-12 10:31:38 -0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2021 Collabora Ltd.
4 * Copyright 2021 BSH Hausgeraete GmbH
5 */
6
7#include "imx8mn.dtsi"
8
9/ {
10 chosen {
11 stdout-path = &uart4;
12 };
13
14 fec_supply: fec_supply_en {
15 compatible = "regulator-fixed";
16 regulator-name = "tja1101_en";
17 regulator-min-microvolt = <3300000>;
18 regulator-max-microvolt = <3300000>;
19 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
20 vin-supply = <&buck4_reg>;
21 enable-active-high;
22 };
23
24 usdhc2_pwrseq: usdhc2_pwrseq {
25 compatible = "mmc-pwrseq-simple";
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_usdhc2_pwrseq>;
28 reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
29 };
30};
31
32&A53_0 {
33 cpu-supply = <&buck2_reg>;
34};
35
36&A53_1 {
37 cpu-supply = <&buck2_reg>;
38};
39
40&A53_2 {
41 cpu-supply = <&buck2_reg>;
42};
43
44&A53_3 {
45 cpu-supply = <&buck2_reg>;
46};
47
48&ecspi2 {
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_espi2>;
51 status = "okay";
52};
53
54&fec1 {
55 pinctrl-names = "default";
56 pinctrl-0 = <&pinctrl_fec1>;
57 phy-mode = "rmii";
58 phy-handle = <&ethphy0>;
59 phy-supply = <&fec_supply>;
60 phy-reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
61 phy-reset-duration = <20>;
62 fsl,magic-packet;
63 status = "okay";
64
65 mdio {
66 #address-cells = <1>;
67 #size-cells = <0>;
68
69 ethphy0: ethernet-phy@0 {
70 compatible = "ethernet-phy-ieee802.3-c22";
71 reg = <0>;
72 };
73 };
74};
75
76&i2c1 {
77 clock-frequency = <400000>;
78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_i2c1>;
80 status = "okay";
81
82 bd71847: pmic@4b {
83 compatible = "rohm,bd71847";
84 reg = <0x4b>;
85 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_pmic>;
87 interrupt-parent = <&gpio1>;
88 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
89 rohm,reset-snvs-powered;
90
91 #clock-cells = <0>;
92 clocks = <&osc_32k 0>;
93 clock-output-names = "clk-32k-out";
94
95 regulators {
96 buck1_reg: BUCK1 {
97 /* PMIC_BUCK1 - VDD_SOC */
98 regulator-name = "buck1";
99 regulator-min-microvolt = <700000>;
100 regulator-max-microvolt = <1300000>;
101 regulator-boot-on;
102 regulator-always-on;
103 regulator-ramp-delay = <1250>;
104 };
105
106 buck2_reg: BUCK2 {
107 /* PMIC_BUCK2 - VDD_ARM */
108 regulator-name = "buck2";
109 regulator-min-microvolt = <700000>;
110 regulator-max-microvolt = <1300000>;
111 regulator-boot-on;
112 regulator-always-on;
113 regulator-ramp-delay = <1250>;
114 };
115
116 buck3_reg: BUCK3 {
117 /* PMIC_BUCK5 - VDD_DRAM_VPU_GPU */
118 regulator-name = "buck3";
119 regulator-min-microvolt = <700000>;
120 regulator-max-microvolt = <1350000>;
121 regulator-boot-on;
122 regulator-always-on;
123 };
124
125 buck4_reg: BUCK4 {
126 /* PMIC_BUCK6 - VDD_3V3 */
127 regulator-name = "buck4";
128 regulator-min-microvolt = <3000000>;
129 regulator-max-microvolt = <3300000>;
130 regulator-boot-on;
131 regulator-always-on;
132 };
133
134 buck5_reg: BUCK5 {
135 /* PMIC_BUCK7 - VDD_1V8 */
136 regulator-name = "buck5";
137 regulator-min-microvolt = <1605000>;
138 regulator-max-microvolt = <1995000>;
139 regulator-boot-on;
140 regulator-always-on;
141 };
142
143 buck6_reg: BUCK6 {
144 /* PMIC_BUCK8 - NVCC_DRAM */
145 regulator-name = "buck6";
146 regulator-min-microvolt = <800000>;
147 regulator-max-microvolt = <1400000>;
148 regulator-boot-on;
149 regulator-always-on;
150 };
151
152 ldo1_reg: LDO1 {
153 /* PMIC_LDO1 - NVCC_SNVS_1V8 */
154 regulator-name = "ldo1";
155 regulator-min-microvolt = <1600000>;
156 regulator-max-microvolt = <1900000>;
157 regulator-boot-on;
158 regulator-always-on;
159 };
160
161 ldo2_reg: LDO2 {
162 /* PMIC_LDO2 - VDD_SNVS_0V8 */
163 regulator-name = "ldo2";
164 regulator-min-microvolt = <800000>;
165 regulator-max-microvolt = <900000>;
166 regulator-boot-on;
167 regulator-always-on;
168 };
169
170 ldo3_reg: LDO3 {
171 /* PMIC_LDO3 - VDDA_1V8 */
172 regulator-name = "ldo3";
173 regulator-min-microvolt = <1800000>;
174 regulator-max-microvolt = <3300000>;
175 regulator-boot-on;
176 regulator-always-on;
177 };
178
179 ldo4_reg: LDO4 {
180 /* PMIC_LDO4 - VDD_MIPI_0V9 */
181 regulator-name = "ldo4";
182 regulator-min-microvolt = <900000>;
183 regulator-max-microvolt = <1800000>;
184 regulator-boot-on;
185 regulator-always-on;
186 };
187
188 ldo6_reg: LDO6 {
189 /* PMIC_LDO6 - VDD_MIPI_1V2 */
190 regulator-name = "ldo6";
191 regulator-min-microvolt = <900000>;
192 regulator-max-microvolt = <1800000>;
193 regulator-boot-on;
194 regulator-always-on;
195 };
196 };
197 };
198};
199
200&i2c3 {
201 clock-frequency = <400000>;
202 pinctrl-names = "default";
203 pinctrl-0 = <&pinctrl_i2c3>;
204 status = "okay";
205};
206
207&i2c4 {
208 clock-frequency = <400000>;
209 pinctrl-names = "default";
210 pinctrl-0 = <&pinctrl_i2c4>;
211 status = "okay";
212};
213
214&uart2 {
215 pinctrl-names = "default";
216 pinctrl-0 = <&pinctrl_uart2>;
217 status = "okay";
218};
219
220&uart3 {
221 pinctrl-names = "default";
222 pinctrl-0 = <&pinctrl_uart3>;
223 assigned-clocks = <&clk IMX8MN_CLK_UART3>;
224 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
225 uart-has-rtscts;
226 status = "okay";
227
228 bluetooth {
229 compatible = "brcm,bcm43438-bt";
230 pinctrl-names = "default";
231 pinctrl-0 = <&pinctrl_bluetooth>;
232 shutdown-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
233 device-wakeup-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
234 host-wakeup-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
235 max-speed = <3000000>;
236 };
237};
238
239/* Console */
240&uart4 {
241 pinctrl-names = "default";
242 pinctrl-0 = <&pinctrl_uart4>;
243 status = "okay";
244};
245
246&usbotg1 {
247 dr_mode = "peripheral";
248 disable-over-current;
249 status = "okay";
250};
251
252&usdhc2 {
253 #address-cells = <1>;
254 #size-cells = <0>;
255 pinctrl-names = "default", "state_100mhz", "state_200mhz";
256 pinctrl-0 = <&pinctrl_usdhc2>;
257 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
258 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
259 mmc-pwrseq = <&usdhc2_pwrseq>;
260 bus-width = <4>;
261 non-removable;
262 status = "okay";
263
264 brcmf: bcrmf@1 {
265 compatible = "brcm,bcm4329-fmac";
266 reg = <1>;
267 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_wlan>;
269 interrupt-parent = <&gpio1>;
270 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
271 interrupt-names = "host-wake";
272 };
273};
274
275&wdog1 {
276 pinctrl-names = "default";
277 pinctrl-0 = <&pinctrl_wdog>;
278 fsl,ext-reset-output;
279 status = "okay";
280};
281
282&iomuxc {
283 pinctrl_espi2: espi2grp {
284 fsl,pins = <
285 MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x082
286 MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x082
287 MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x082
288 MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x040
289 >;
290 };
291
292 pinctrl_i2c1: i2c1grp {
293 fsl,pins = <
294 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400000c2
295 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400000c2
296 >;
297 };
298
299 pinctrl_i2c3: i2c3grp {
300 fsl,pins = <
301 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400000c2
302 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400000c2
303 >;
304 };
305
306 pinctrl_i2c4: i2c4grp {
307 fsl,pins = <
308 MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400000c2
309 MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400000c2
310 >;
311 };
312
313 pinctrl_pmic: pmicirq {
314 fsl,pins = <
315 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x040
316 >;
317 };
318
319 pinctrl_uart4: uart4grp {
320 fsl,pins = <
321 MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x040
322 MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x040
323 >;
324 };
325
326 pinctrl_usdhc2_pwrseq: usdhc2pwrseqgrp {
327 fsl,pins = <
328 MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x040 /* WL_REG_ON */
329 >;
330 };
331
332 pinctrl_usdhc2: usdhc2grp {
333 fsl,pins = <
334 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x090
335 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d0
336 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d0
337 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d0
338 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d0
339 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d0
340 >;
341 };
342
343 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
344 fsl,pins = <
345 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x094
346 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d4
347 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d4
348 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d4
349 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d4
350 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d4
351 >;
352 };
353
354 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
355 fsl,pins = <
356 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x096
357 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d6
358 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d6
359 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d6
360 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d6
361 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d6
362 >;
363 };
364
365 pinctrl_wlan: wlangrp {
366 fsl,pins = <
367 MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x0d6 /* GPIO_0 - WIFI_GPIO_0 */
368 MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x0d6 /* GPIO_1 - WIFI_GPIO_1 */
369 MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x0d6 /* BT_GPIO_5 - WIFI_GPIO_5 */
370 MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x0d6 /* I2S_CLK - WIFI_GPIO_6 */
371 >;
372 };
373
374 pinctrl_uart2: uart2grp {
375 fsl,pins = <
376 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x040
377 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x040
378 >;
379 };
380
381 pinctrl_uart3: uart3grp {
382 fsl,pins = <
383 MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x040
384 MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x040
385 MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x040
386 MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x040
387 >;
388 };
389
390 pinctrl_bluetooth: bluetoothgrp {
391 fsl,pins = <
392 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x044 /* BT_REG_ON */
393 MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x046 /* BT_DEV_WAKE */
394 MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x090 /* BT_HOST_WAKE */
395 >;
396 };
397
398 pinctrl_wdog: wdoggrp {
399 fsl,pins = <
400 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x046
401 >;
402 };
403
404 pinctrl_fec1: fec1grp {
405 fsl,pins = <
406 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x002
407 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x002
408 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090
409 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x090
410 MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER 0x090
411 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x016
412 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x016
413 MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x016
414 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x016
415 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x090
416 MX8MN_IOMUXC_ENET_TXC_ENET1_TX_ER 0x016
417 MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x150 /* RMII_INT - ENET_INT */
418 MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x150 /* RMII_EN - ENET_EN */
419 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x016 /* RMII_WAKE - GPIO_ENET_WAKE */
420 MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x016 /* RMII_RESET - GPIO_ENET_RST */
421 >;
422 };
423};