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git01.mediatek.com / filogic / uboot / bd46e0eec0db6c887dde7e05b82347fbdab761f5 / . / arch / arm / dts / dra7.dtsi
blob: 8f1e25bcecbd76273f62671e8b9afa8f193ea261 [file] [log] [blame]
Tom Rinie33af1c2015-07-31 19:55:12 -0400[diff] [blame]1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/pinctrl/dra.h>
12
13#include "skeleton.dtsi"
14
15#define MAX_SOURCES 400
16
17/ {
18 #address-cells = <1>;
19 #size-cells = <1>;
20
21 compatible = "ti,dra7xx";
22 interrupt-parent = <&crossbar_mpu>;
23
24 aliases {
25 i2c0 = &i2c1;
26 i2c1 = &i2c2;
27 i2c2 = &i2c3;
28 i2c3 = &i2c4;
29 i2c4 = &i2c5;
30 serial0 = &uart1;
31 serial1 = &uart2;
32 serial2 = &uart3;
33 serial3 = &uart4;
34 serial4 = &uart5;
35 serial5 = &uart6;
36 serial6 = &uart7;
37 serial7 = &uart8;
38 serial8 = &uart9;
39 serial9 = &uart10;
40 ethernet0 = &cpsw_emac0;
41 ethernet1 = &cpsw_emac1;
42 d_can0 = &dcan1;
43 d_can1 = &dcan2;
44 };
45
46 timer {
47 compatible = "arm,armv7-timer";
48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
52 interrupt-parent = <&gic>;
53 };
54
55 gic: interrupt-controller@48211000 {
56 compatible = "arm,cortex-a15-gic";
57 interrupt-controller;
58 #interrupt-cells = <3>;
59 reg = <0x48211000 0x1000>,
60 <0x48212000 0x1000>,
61 <0x48214000 0x2000>,
62 <0x48216000 0x2000>;
63 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
64 interrupt-parent = <&gic>;
65 };
66
67 wakeupgen: interrupt-controller@48281000 {
68 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
69 interrupt-controller;
70 #interrupt-cells = <3>;
71 reg = <0x48281000 0x1000>;
72 interrupt-parent = <&gic>;
73 };
74
75 /*
76 * The soc node represents the soc top level view. It is used for IPs
77 * that are not memory mapped in the MPU view or for the MPU itself.
78 */
79 soc {
80 compatible = "ti,omap-infra";
81 mpu {
82 compatible = "ti,omap5-mpu";
83 ti,hwmods = "mpu";
84 };
85 };
86
87 /*
88 * XXX: Use a flat representation of the SOC interconnect.
89 * The real OMAP interconnect network is quite complex.
90 * Since it will not bring real advantage to represent that in DT for
91 * the moment, just use a fake OCP bus entry to represent the whole bus
92 * hierarchy.
93 */
94 ocp {
95 compatible = "ti,dra7-l3-noc", "simple-bus";
96 #address-cells = <1>;
97 #size-cells = <1>;
98 ranges;
99 ti,hwmods = "l3_main_1", "l3_main_2";
100 reg = <0x44000000 0x1000000>,
101 <0x45000000 0x1000>;
102 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
103 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
104
105 l4_cfg: l4@4a000000 {
106 compatible = "ti,dra7-l4-cfg", "simple-bus";
107 #address-cells = <1>;
108 #size-cells = <1>;
109 ranges = <0 0x4a000000 0x22c000>;
110
111 scm: scm@2000 {
112 compatible = "ti,dra7-scm-core", "simple-bus";
113 reg = <0x2000 0x2000>;
114 #address-cells = <1>;
115 #size-cells = <1>;
116 ranges = <0 0x2000 0x2000>;
117
118 scm_conf: scm_conf@0 {
119 compatible = "syscon";
120 reg = <0x0 0x1400>;
121 #address-cells = <1>;
122 #size-cells = <1>;
123
124 pbias_regulator: pbias_regulator {
125 compatible = "ti,pbias-omap";
126 reg = <0xe00 0x4>;
127 syscon = <&scm_conf>;
128 pbias_mmc_reg: pbias_mmc_omap5 {
129 regulator-name = "pbias_mmc_omap5";
130 regulator-min-microvolt = <1800000>;
131 regulator-max-microvolt = <3000000>;
132 };
133 };
134
135 scm_conf_clocks: clocks {
136 #address-cells = <1>;
137 #size-cells = <0>;
138 };
139 };
140
141 dra7_pmx_core: pinmux@1400 {
142 compatible = "ti,dra7-padconf",
143 "pinctrl-single";
144 reg = <0x1400 0x0464>;
145 #address-cells = <1>;
146 #size-cells = <0>;
147 #interrupt-cells = <1>;
148 interrupt-controller;
149 pinctrl-single,register-width = <32>;
150 pinctrl-single,function-mask = <0x3fffffff>;
151 };
152 };
153
154 cm_core_aon: cm_core_aon@5000 {
155 compatible = "ti,dra7-cm-core-aon";
156 reg = <0x5000 0x2000>;
157
158 cm_core_aon_clocks: clocks {
159 #address-cells = <1>;
160 #size-cells = <0>;
161 };
162
163 cm_core_aon_clockdomains: clockdomains {
164 };
165 };
166
167 cm_core: cm_core@8000 {
168 compatible = "ti,dra7-cm-core";
169 reg = <0x8000 0x3000>;
170
171 cm_core_clocks: clocks {
172 #address-cells = <1>;
173 #size-cells = <0>;
174 };
175
176 cm_core_clockdomains: clockdomains {
177 };
178 };
179 };
180
181 l4_wkup: l4@4ae00000 {
182 compatible = "ti,dra7-l4-wkup", "simple-bus";
183 #address-cells = <1>;
184 #size-cells = <1>;
185 ranges = <0 0x4ae00000 0x3f000>;
186
187 counter32k: counter@4000 {
188 compatible = "ti,omap-counter32k";
189 reg = <0x4000 0x40>;
190 ti,hwmods = "counter_32k";
191 };
192
193 prm: prm@6000 {
194 compatible = "ti,dra7-prm";
195 reg = <0x6000 0x3000>;
196 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
197
198 prm_clocks: clocks {
199 #address-cells = <1>;
200 #size-cells = <0>;
201 };
202
203 prm_clockdomains: clockdomains {
204 };
205 };
206 };
207
208 axi@0 {
209 compatible = "simple-bus";
210 #size-cells = <1>;
211 #address-cells = <1>;
212 ranges = <0x51000000 0x51000000 0x3000
213 0x0 0x20000000 0x10000000>;
214 pcie@51000000 {
215 compatible = "ti,dra7-pcie";
216 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
217 reg-names = "rc_dbics", "ti_conf", "config";
218 interrupts = <0 232 0x4>, <0 233 0x4>;
219 #address-cells = <3>;
220 #size-cells = <2>;
221 device_type = "pci";
222 ranges = <0x81000000 0 0 0x03000 0 0x00010000
223 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
224 #interrupt-cells = <1>;
225 num-lanes = <1>;
226 ti,hwmods = "pcie1";
227 phys = <&pcie1_phy>;
228 phy-names = "pcie-phy0";
229 interrupt-map-mask = <0 0 0 7>;
230 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
231 <0 0 0 2 &pcie1_intc 2>,
232 <0 0 0 3 &pcie1_intc 3>,
233 <0 0 0 4 &pcie1_intc 4>;
234 pcie1_intc: interrupt-controller {
235 interrupt-controller;
236 #address-cells = <0>;
237 #interrupt-cells = <1>;
238 };
239 };
240 };
241
242 axi@1 {
243 compatible = "simple-bus";
244 #size-cells = <1>;
245 #address-cells = <1>;
246 ranges = <0x51800000 0x51800000 0x3000
247 0x0 0x30000000 0x10000000>;
248 status = "disabled";
249 pcie@51000000 {
250 compatible = "ti,dra7-pcie";
251 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
252 reg-names = "rc_dbics", "ti_conf", "config";
253 interrupts = <0 355 0x4>, <0 356 0x4>;
254 #address-cells = <3>;
255 #size-cells = <2>;
256 device_type = "pci";
257 ranges = <0x81000000 0 0 0x03000 0 0x00010000
258 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
259 #interrupt-cells = <1>;
260 num-lanes = <1>;
261 ti,hwmods = "pcie2";
262 phys = <&pcie2_phy>;
263 phy-names = "pcie-phy0";
264 interrupt-map-mask = <0 0 0 7>;
265 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
266 <0 0 0 2 &pcie2_intc 2>,
267 <0 0 0 3 &pcie2_intc 3>,
268 <0 0 0 4 &pcie2_intc 4>;
269 pcie2_intc: interrupt-controller {
270 interrupt-controller;
271 #address-cells = <0>;
272 #interrupt-cells = <1>;
273 };
274 };
275 };
276
277 bandgap: bandgap@4a0021e0 {
278 reg = <0x4a0021e0 0xc
279 0x4a00232c 0xc
280 0x4a002380 0x2c
281 0x4a0023C0 0x3c
282 0x4a002564 0x8
283 0x4a002574 0x50>;
284 compatible = "ti,dra752-bandgap";
285 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
286 #thermal-sensor-cells = <1>;
287 };
288
289 dra7_ctrl_core: ctrl_core@4a002000 {
290 compatible = "syscon";
291 reg = <0x4a002000 0x6d0>;
292 };
293
294 dra7_ctrl_general: tisyscon@4a002e00 {
295 compatible = "syscon";
296 reg = <0x4a002e00 0x7c>;
297 };
298
299 sdma: dma-controller@4a056000 {
300 compatible = "ti,omap4430-sdma";
301 reg = <0x4a056000 0x1000>;
302 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
306 #dma-cells = <1>;
307 dma-channels = <32>;
308 dma-requests = <127>;
309 };
310
311 gpio1: gpio@4ae10000 {
312 compatible = "ti,omap4-gpio";
313 reg = <0x4ae10000 0x200>;
314 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
315 ti,hwmods = "gpio1";
316 gpio-controller;
317 #gpio-cells = <2>;
318 interrupt-controller;
319 #interrupt-cells = <2>;
320 };
321
322 gpio2: gpio@48055000 {
323 compatible = "ti,omap4-gpio";
324 reg = <0x48055000 0x200>;
325 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
326 ti,hwmods = "gpio2";
327 gpio-controller;
328 #gpio-cells = <2>;
329 interrupt-controller;
330 #interrupt-cells = <2>;
331 };
332
333 gpio3: gpio@48057000 {
334 compatible = "ti,omap4-gpio";
335 reg = <0x48057000 0x200>;
336 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
337 ti,hwmods = "gpio3";
338 gpio-controller;
339 #gpio-cells = <2>;
340 interrupt-controller;
341 #interrupt-cells = <2>;
342 };
343
344 gpio4: gpio@48059000 {
345 compatible = "ti,omap4-gpio";
346 reg = <0x48059000 0x200>;
347 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
348 ti,hwmods = "gpio4";
349 gpio-controller;
350 #gpio-cells = <2>;
351 interrupt-controller;
352 #interrupt-cells = <2>;
353 };
354
355 gpio5: gpio@4805b000 {
356 compatible = "ti,omap4-gpio";
357 reg = <0x4805b000 0x200>;
358 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
359 ti,hwmods = "gpio5";
360 gpio-controller;
361 #gpio-cells = <2>;
362 interrupt-controller;
363 #interrupt-cells = <2>;
364 };
365
366 gpio6: gpio@4805d000 {
367 compatible = "ti,omap4-gpio";
368 reg = <0x4805d000 0x200>;
369 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
370 ti,hwmods = "gpio6";
371 gpio-controller;
372 #gpio-cells = <2>;
373 interrupt-controller;
374 #interrupt-cells = <2>;
375 };
376
377 gpio7: gpio@48051000 {
378 compatible = "ti,omap4-gpio";
379 reg = <0x48051000 0x200>;
380 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
381 ti,hwmods = "gpio7";
382 gpio-controller;
383 #gpio-cells = <2>;
384 interrupt-controller;
385 #interrupt-cells = <2>;
386 };
387
388 gpio8: gpio@48053000 {
389 compatible = "ti,omap4-gpio";
390 reg = <0x48053000 0x200>;
391 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
392 ti,hwmods = "gpio8";
393 gpio-controller;
394 #gpio-cells = <2>;
395 interrupt-controller;
396 #interrupt-cells = <2>;
397 };
398
399 uart1: serial@4806a000 {
400 compatible = "ti,omap4-uart";
401 reg = <0x4806a000 0x100>;
402 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
403 ti,hwmods = "uart1";
404 clock-frequency = <48000000>;
405 status = "disabled";
406 dmas = <&sdma 49>, <&sdma 50>;
407 dma-names = "tx", "rx";
408 };
409
410 uart2: serial@4806c000 {
411 compatible = "ti,omap4-uart";
412 reg = <0x4806c000 0x100>;
413 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
414 ti,hwmods = "uart2";
415 clock-frequency = <48000000>;
416 status = "disabled";
417 dmas = <&sdma 51>, <&sdma 52>;
418 dma-names = "tx", "rx";
419 };
420
421 uart3: serial@48020000 {
422 compatible = "ti,omap4-uart";
423 reg = <0x48020000 0x100>;
424 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
425 ti,hwmods = "uart3";
426 clock-frequency = <48000000>;
427 status = "disabled";
428 dmas = <&sdma 53>, <&sdma 54>;
429 dma-names = "tx", "rx";
430 };
431
432 uart4: serial@4806e000 {
433 compatible = "ti,omap4-uart";
434 reg = <0x4806e000 0x100>;
435 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
436 ti,hwmods = "uart4";
437 clock-frequency = <48000000>;
438 status = "disabled";
439 dmas = <&sdma 55>, <&sdma 56>;
440 dma-names = "tx", "rx";
441 };
442
443 uart5: serial@48066000 {
444 compatible = "ti,omap4-uart";
445 reg = <0x48066000 0x100>;
446 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
447 ti,hwmods = "uart5";
448 clock-frequency = <48000000>;
449 status = "disabled";
450 dmas = <&sdma 63>, <&sdma 64>;
451 dma-names = "tx", "rx";
452 };
453
454 uart6: serial@48068000 {
455 compatible = "ti,omap4-uart";
456 reg = <0x48068000 0x100>;
457 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
458 ti,hwmods = "uart6";
459 clock-frequency = <48000000>;
460 status = "disabled";
461 dmas = <&sdma 79>, <&sdma 80>;
462 dma-names = "tx", "rx";
463 };
464
465 uart7: serial@48420000 {
466 compatible = "ti,omap4-uart";
467 reg = <0x48420000 0x100>;
468 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
469 ti,hwmods = "uart7";
470 clock-frequency = <48000000>;
471 status = "disabled";
472 };
473
474 uart8: serial@48422000 {
475 compatible = "ti,omap4-uart";
476 reg = <0x48422000 0x100>;
477 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
478 ti,hwmods = "uart8";
479 clock-frequency = <48000000>;
480 status = "disabled";
481 };
482
483 uart9: serial@48424000 {
484 compatible = "ti,omap4-uart";
485 reg = <0x48424000 0x100>;
486 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
487 ti,hwmods = "uart9";
488 clock-frequency = <48000000>;
489 status = "disabled";
490 };
491
492 uart10: serial@4ae2b000 {
493 compatible = "ti,omap4-uart";
494 reg = <0x4ae2b000 0x100>;
495 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
496 ti,hwmods = "uart10";
497 clock-frequency = <48000000>;
498 status = "disabled";
499 };
500
501 mailbox1: mailbox@4a0f4000 {
502 compatible = "ti,omap4-mailbox";
503 reg = <0x4a0f4000 0x200>;
504 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
507 ti,hwmods = "mailbox1";
508 #mbox-cells = <1>;
509 ti,mbox-num-users = <3>;
510 ti,mbox-num-fifos = <8>;
511 status = "disabled";
512 };
513
514 mailbox2: mailbox@4883a000 {
515 compatible = "ti,omap4-mailbox";
516 reg = <0x4883a000 0x200>;
517 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
518 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
521 ti,hwmods = "mailbox2";
522 #mbox-cells = <1>;
523 ti,mbox-num-users = <4>;
524 ti,mbox-num-fifos = <12>;
525 status = "disabled";
526 };
527
528 mailbox3: mailbox@4883c000 {
529 compatible = "ti,omap4-mailbox";
530 reg = <0x4883c000 0x200>;
531 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
535 ti,hwmods = "mailbox3";
536 #mbox-cells = <1>;
537 ti,mbox-num-users = <4>;
538 ti,mbox-num-fifos = <12>;
539 status = "disabled";
540 };
541
542 mailbox4: mailbox@4883e000 {
543 compatible = "ti,omap4-mailbox";
544 reg = <0x4883e000 0x200>;
545 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
546 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
547 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
548 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
549 ti,hwmods = "mailbox4";
550 #mbox-cells = <1>;
551 ti,mbox-num-users = <4>;
552 ti,mbox-num-fifos = <12>;
553 status = "disabled";
554 };
555
556 mailbox5: mailbox@48840000 {
557 compatible = "ti,omap4-mailbox";
558 reg = <0x48840000 0x200>;
559 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
560 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
563 ti,hwmods = "mailbox5";
564 #mbox-cells = <1>;
565 ti,mbox-num-users = <4>;
566 ti,mbox-num-fifos = <12>;
567 status = "disabled";
568 };
569
570 mailbox6: mailbox@48842000 {
571 compatible = "ti,omap4-mailbox";
572 reg = <0x48842000 0x200>;
573 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
574 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
575 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
576 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
577 ti,hwmods = "mailbox6";
578 #mbox-cells = <1>;
579 ti,mbox-num-users = <4>;
580 ti,mbox-num-fifos = <12>;
581 status = "disabled";
582 };
583
584 mailbox7: mailbox@48844000 {
585 compatible = "ti,omap4-mailbox";
586 reg = <0x48844000 0x200>;
587 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
588 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
591 ti,hwmods = "mailbox7";
592 #mbox-cells = <1>;
593 ti,mbox-num-users = <4>;
594 ti,mbox-num-fifos = <12>;
595 status = "disabled";
596 };
597
598 mailbox8: mailbox@48846000 {
599 compatible = "ti,omap4-mailbox";
600 reg = <0x48846000 0x200>;
601 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
602 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
603 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
605 ti,hwmods = "mailbox8";
606 #mbox-cells = <1>;
607 ti,mbox-num-users = <4>;
608 ti,mbox-num-fifos = <12>;
609 status = "disabled";
610 };
611
612 mailbox9: mailbox@4885e000 {
613 compatible = "ti,omap4-mailbox";
614 reg = <0x4885e000 0x200>;
615 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
616 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
617 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
618 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
619 ti,hwmods = "mailbox9";
620 #mbox-cells = <1>;
621 ti,mbox-num-users = <4>;
622 ti,mbox-num-fifos = <12>;
623 status = "disabled";
624 };
625
626 mailbox10: mailbox@48860000 {
627 compatible = "ti,omap4-mailbox";
628 reg = <0x48860000 0x200>;
629 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
630 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
631 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
632 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
633 ti,hwmods = "mailbox10";
634 #mbox-cells = <1>;
635 ti,mbox-num-users = <4>;
636 ti,mbox-num-fifos = <12>;
637 status = "disabled";
638 };
639
640 mailbox11: mailbox@48862000 {
641 compatible = "ti,omap4-mailbox";
642 reg = <0x48862000 0x200>;
643 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
644 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
645 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
646 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
647 ti,hwmods = "mailbox11";
648 #mbox-cells = <1>;
649 ti,mbox-num-users = <4>;
650 ti,mbox-num-fifos = <12>;
651 status = "disabled";
652 };
653
654 mailbox12: mailbox@48864000 {
655 compatible = "ti,omap4-mailbox";
656 reg = <0x48864000 0x200>;
657 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
658 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
659 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
660 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
661 ti,hwmods = "mailbox12";
662 #mbox-cells = <1>;
663 ti,mbox-num-users = <4>;
664 ti,mbox-num-fifos = <12>;
665 status = "disabled";
666 };
667
668 mailbox13: mailbox@48802000 {
669 compatible = "ti,omap4-mailbox";
670 reg = <0x48802000 0x200>;
671 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
672 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
673 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
674 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
675 ti,hwmods = "mailbox13";
676 #mbox-cells = <1>;
677 ti,mbox-num-users = <4>;
678 ti,mbox-num-fifos = <12>;
679 status = "disabled";
680 };
681
682 timer1: timer@4ae18000 {
683 compatible = "ti,omap5430-timer";
684 reg = <0x4ae18000 0x80>;
685 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
686 ti,hwmods = "timer1";
687 ti,timer-alwon;
688 };
689
690 timer2: timer@48032000 {
691 compatible = "ti,omap5430-timer";
692 reg = <0x48032000 0x80>;
693 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
694 ti,hwmods = "timer2";
695 };
696
697 timer3: timer@48034000 {
698 compatible = "ti,omap5430-timer";
699 reg = <0x48034000 0x80>;
700 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
701 ti,hwmods = "timer3";
702 };
703
704 timer4: timer@48036000 {
705 compatible = "ti,omap5430-timer";
706 reg = <0x48036000 0x80>;
707 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
708 ti,hwmods = "timer4";
709 };
710
711 timer5: timer@48820000 {
712 compatible = "ti,omap5430-timer";
713 reg = <0x48820000 0x80>;
714 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
715 ti,hwmods = "timer5";
716 };
717
718 timer6: timer@48822000 {
719 compatible = "ti,omap5430-timer";
720 reg = <0x48822000 0x80>;
721 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
722 ti,hwmods = "timer6";
723 };
724
725 timer7: timer@48824000 {
726 compatible = "ti,omap5430-timer";
727 reg = <0x48824000 0x80>;
728 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
729 ti,hwmods = "timer7";
730 };
731
732 timer8: timer@48826000 {
733 compatible = "ti,omap5430-timer";
734 reg = <0x48826000 0x80>;
735 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
736 ti,hwmods = "timer8";
737 };
738
739 timer9: timer@4803e000 {
740 compatible = "ti,omap5430-timer";
741 reg = <0x4803e000 0x80>;
742 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
743 ti,hwmods = "timer9";
744 };
745
746 timer10: timer@48086000 {
747 compatible = "ti,omap5430-timer";
748 reg = <0x48086000 0x80>;
749 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
750 ti,hwmods = "timer10";
751 };
752
753 timer11: timer@48088000 {
754 compatible = "ti,omap5430-timer";
755 reg = <0x48088000 0x80>;
756 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
757 ti,hwmods = "timer11";
758 };
759
760 timer13: timer@48828000 {
761 compatible = "ti,omap5430-timer";
762 reg = <0x48828000 0x80>;
763 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
764 ti,hwmods = "timer13";
765 status = "disabled";
766 };
767
768 timer14: timer@4882a000 {
769 compatible = "ti,omap5430-timer";
770 reg = <0x4882a000 0x80>;
771 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
772 ti,hwmods = "timer14";
773 status = "disabled";
774 };
775
776 timer15: timer@4882c000 {
777 compatible = "ti,omap5430-timer";
778 reg = <0x4882c000 0x80>;
779 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
780 ti,hwmods = "timer15";
781 status = "disabled";
782 };
783
784 timer16: timer@4882e000 {
785 compatible = "ti,omap5430-timer";
786 reg = <0x4882e000 0x80>;
787 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
788 ti,hwmods = "timer16";
789 status = "disabled";
790 };
791
792 wdt2: wdt@4ae14000 {
793 compatible = "ti,omap3-wdt";
794 reg = <0x4ae14000 0x80>;
795 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
796 ti,hwmods = "wd_timer2";
797 };
798
799 hwspinlock: spinlock@4a0f6000 {
800 compatible = "ti,omap4-hwspinlock";
801 reg = <0x4a0f6000 0x1000>;
802 ti,hwmods = "spinlock";
803 #hwlock-cells = <1>;
804 };
805
806 dmm@4e000000 {
807 compatible = "ti,omap5-dmm";
808 reg = <0x4e000000 0x800>;
809 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
810 ti,hwmods = "dmm";
811 };
812
813 i2c1: i2c@48070000 {
814 compatible = "ti,omap4-i2c";
815 reg = <0x48070000 0x100>;
816 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
817 #address-cells = <1>;
818 #size-cells = <0>;
819 ti,hwmods = "i2c1";
820 status = "disabled";
821 };
822
823 i2c2: i2c@48072000 {
824 compatible = "ti,omap4-i2c";
825 reg = <0x48072000 0x100>;
826 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
827 #address-cells = <1>;
828 #size-cells = <0>;
829 ti,hwmods = "i2c2";
830 status = "disabled";
831 };
832
833 i2c3: i2c@48060000 {
834 compatible = "ti,omap4-i2c";
835 reg = <0x48060000 0x100>;
836 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
837 #address-cells = <1>;
838 #size-cells = <0>;
839 ti,hwmods = "i2c3";
840 status = "disabled";
841 };
842
843 i2c4: i2c@4807a000 {
844 compatible = "ti,omap4-i2c";
845 reg = <0x4807a000 0x100>;
846 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
847 #address-cells = <1>;
848 #size-cells = <0>;
849 ti,hwmods = "i2c4";
850 status = "disabled";
851 };
852
853 i2c5: i2c@4807c000 {
854 compatible = "ti,omap4-i2c";
855 reg = <0x4807c000 0x100>;
856 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
857 #address-cells = <1>;
858 #size-cells = <0>;
859 ti,hwmods = "i2c5";
860 status = "disabled";
861 };
862
863 mmc1: mmc@4809c000 {
864 compatible = "ti,omap4-hsmmc";
865 reg = <0x4809c000 0x400>;
866 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
867 ti,hwmods = "mmc1";
868 ti,dual-volt;
869 ti,needs-special-reset;
870 dmas = <&sdma 61>, <&sdma 62>;
871 dma-names = "tx", "rx";
872 status = "disabled";
873 pbias-supply = <&pbias_mmc_reg>;
874 };
875
876 mmc2: mmc@480b4000 {
877 compatible = "ti,omap4-hsmmc";
878 reg = <0x480b4000 0x400>;
879 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
880 ti,hwmods = "mmc2";
881 ti,needs-special-reset;
882 dmas = <&sdma 47>, <&sdma 48>;
883 dma-names = "tx", "rx";
884 status = "disabled";
885 };
886
887 mmc3: mmc@480ad000 {
888 compatible = "ti,omap4-hsmmc";
889 reg = <0x480ad000 0x400>;
890 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
891 ti,hwmods = "mmc3";
892 ti,needs-special-reset;
893 dmas = <&sdma 77>, <&sdma 78>;
894 dma-names = "tx", "rx";
895 status = "disabled";
896 };
897
898 mmc4: mmc@480d1000 {
899 compatible = "ti,omap4-hsmmc";
900 reg = <0x480d1000 0x400>;
901 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
902 ti,hwmods = "mmc4";
903 ti,needs-special-reset;
904 dmas = <&sdma 57>, <&sdma 58>;
905 dma-names = "tx", "rx";
906 status = "disabled";
907 };
908
909 abb_mpu: regulator-abb-mpu {
910 compatible = "ti,abb-v3";
911 regulator-name = "abb_mpu";
912 #address-cells = <0>;
913 #size-cells = <0>;
914 clocks = <&sys_clkin1>;
915 ti,settling-time = <50>;
916 ti,clock-cycles = <16>;
917
918 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
919 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
920 <0x4ae0c158 0x4>;
921 reg-names = "setup-address", "control-address",
922 "int-address", "efuse-address",
923 "ldo-address";
924 ti,tranxdone-status-mask = <0x80>;
925 /* LDOVBBMPU_FBB_MUX_CTRL */
926 ti,ldovbb-override-mask = <0x400>;
927 /* LDOVBBMPU_FBB_VSET_OUT */
928 ti,ldovbb-vset-mask = <0x1F>;
929
930 /*
931 * NOTE: only FBB mode used but actual vset will
932 * determine final biasing
933 */
934 ti,abb_info = <
935 /*uV ABB efuse rbb_m fbb_m vset_m*/
936 1060000 0 0x0 0 0x02000000 0x01F00000
937 1160000 0 0x4 0 0x02000000 0x01F00000
938 1210000 0 0x8 0 0x02000000 0x01F00000
939 >;
940 };
941
942 abb_ivahd: regulator-abb-ivahd {
943 compatible = "ti,abb-v3";
944 regulator-name = "abb_ivahd";
945 #address-cells = <0>;
946 #size-cells = <0>;
947 clocks = <&sys_clkin1>;
948 ti,settling-time = <50>;
949 ti,clock-cycles = <16>;
950
951 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
952 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
953 <0x4a002470 0x4>;
954 reg-names = "setup-address", "control-address",
955 "int-address", "efuse-address",
956 "ldo-address";
957 ti,tranxdone-status-mask = <0x40000000>;
958 /* LDOVBBIVA_FBB_MUX_CTRL */
959 ti,ldovbb-override-mask = <0x400>;
960 /* LDOVBBIVA_FBB_VSET_OUT */
961 ti,ldovbb-vset-mask = <0x1F>;
962
963 /*
964 * NOTE: only FBB mode used but actual vset will
965 * determine final biasing
966 */
967 ti,abb_info = <
968 /*uV ABB efuse rbb_m fbb_m vset_m*/
969 1055000 0 0x0 0 0x02000000 0x01F00000
970 1150000 0 0x4 0 0x02000000 0x01F00000
971 1250000 0 0x8 0 0x02000000 0x01F00000
972 >;
973 };
974
975 abb_dspeve: regulator-abb-dspeve {
976 compatible = "ti,abb-v3";
977 regulator-name = "abb_dspeve";
978 #address-cells = <0>;
979 #size-cells = <0>;
980 clocks = <&sys_clkin1>;
981 ti,settling-time = <50>;
982 ti,clock-cycles = <16>;
983
984 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
985 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
986 <0x4a00246c 0x4>;
987 reg-names = "setup-address", "control-address",
988 "int-address", "efuse-address",
989 "ldo-address";
990 ti,tranxdone-status-mask = <0x20000000>;
991 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
992 ti,ldovbb-override-mask = <0x400>;
993 /* LDOVBBDSPEVE_FBB_VSET_OUT */
994 ti,ldovbb-vset-mask = <0x1F>;
995
996 /*
997 * NOTE: only FBB mode used but actual vset will
998 * determine final biasing
999 */
1000 ti,abb_info = <
1001 /*uV ABB efuse rbb_m fbb_m vset_m*/
1002 1055000 0 0x0 0 0x02000000 0x01F00000
1003 1150000 0 0x4 0 0x02000000 0x01F00000
1004 1250000 0 0x8 0 0x02000000 0x01F00000
1005 >;
1006 };
1007
1008 abb_gpu: regulator-abb-gpu {
1009 compatible = "ti,abb-v3";
1010 regulator-name = "abb_gpu";
1011 #address-cells = <0>;
1012 #size-cells = <0>;
1013 clocks = <&sys_clkin1>;
1014 ti,settling-time = <50>;
1015 ti,clock-cycles = <16>;
1016
1017 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
1018 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
1019 <0x4ae0c154 0x4>;
1020 reg-names = "setup-address", "control-address",
1021 "int-address", "efuse-address",
1022 "ldo-address";
1023 ti,tranxdone-status-mask = <0x10000000>;
1024 /* LDOVBBGPU_FBB_MUX_CTRL */
1025 ti,ldovbb-override-mask = <0x400>;
1026 /* LDOVBBGPU_FBB_VSET_OUT */
1027 ti,ldovbb-vset-mask = <0x1F>;
1028
1029 /*
1030 * NOTE: only FBB mode used but actual vset will
1031 * determine final biasing
1032 */
1033 ti,abb_info = <
1034 /*uV ABB efuse rbb_m fbb_m vset_m*/
1035 1090000 0 0x0 0 0x02000000 0x01F00000
1036 1210000 0 0x4 0 0x02000000 0x01F00000
1037 1280000 0 0x8 0 0x02000000 0x01F00000
1038 >;
1039 };
1040
1041 mcspi1: spi@48098000 {
1042 compatible = "ti,omap4-mcspi";
1043 reg = <0x48098000 0x200>;
1044 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1045 #address-cells = <1>;
1046 #size-cells = <0>;
1047 ti,hwmods = "mcspi1";
1048 ti,spi-num-cs = <4>;
1049 dmas = <&sdma 35>,
1050 <&sdma 36>,
1051 <&sdma 37>,
1052 <&sdma 38>,
1053 <&sdma 39>,
1054 <&sdma 40>,
1055 <&sdma 41>,
1056 <&sdma 42>;
1057 dma-names = "tx0", "rx0", "tx1", "rx1",
1058 "tx2", "rx2", "tx3", "rx3";
1059 status = "disabled";
1060 };
1061
1062 mcspi2: spi@4809a000 {
1063 compatible = "ti,omap4-mcspi";
1064 reg = <0x4809a000 0x200>;
1065 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1066 #address-cells = <1>;
1067 #size-cells = <0>;
1068 ti,hwmods = "mcspi2";
1069 ti,spi-num-cs = <2>;
1070 dmas = <&sdma 43>,
1071 <&sdma 44>,
1072 <&sdma 45>,
1073 <&sdma 46>;
1074 dma-names = "tx0", "rx0", "tx1", "rx1";
1075 status = "disabled";
1076 };
1077
1078 mcspi3: spi@480b8000 {
1079 compatible = "ti,omap4-mcspi";
1080 reg = <0x480b8000 0x200>;
1081 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1082 #address-cells = <1>;
1083 #size-cells = <0>;
1084 ti,hwmods = "mcspi3";
1085 ti,spi-num-cs = <2>;
1086 dmas = <&sdma 15>, <&sdma 16>;
1087 dma-names = "tx0", "rx0";
1088 status = "disabled";
1089 };
1090
1091 mcspi4: spi@480ba000 {
1092 compatible = "ti,omap4-mcspi";
1093 reg = <0x480ba000 0x200>;
1094 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1095 #address-cells = <1>;
1096 #size-cells = <0>;
1097 ti,hwmods = "mcspi4";
1098 ti,spi-num-cs = <1>;
1099 dmas = <&sdma 70>, <&sdma 71>;
1100 dma-names = "tx0", "rx0";
1101 status = "disabled";
1102 };
1103
1104 qspi: qspi@4b300000 {
1105 compatible = "ti,dra7xxx-qspi";
1106 reg = <0x4b300000 0x100>;
1107 reg-names = "qspi_base";
1108 #address-cells = <1>;
1109 #size-cells = <0>;
1110 ti,hwmods = "qspi";
1111 clocks = <&qspi_gfclk_div>;
1112 clock-names = "fck";
1113 num-cs = <4>;
1114 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1115 status = "disabled";
1116 };
1117
1118 omap_control_sata: control-phy@4a002374 {
1119 compatible = "ti,control-phy-pipe3";
1120 reg = <0x4a002374 0x4>;
1121 reg-names = "power";
1122 clocks = <&sys_clkin1>;
1123 clock-names = "sysclk";
1124 };
1125
1126 /* OCP2SCP3 */
1127 ocp2scp@4a090000 {
1128 compatible = "ti,omap-ocp2scp";
1129 #address-cells = <1>;
1130 #size-cells = <1>;
1131 ranges;
1132 reg = <0x4a090000 0x20>;
1133 ti,hwmods = "ocp2scp3";
1134 sata_phy: phy@4A096000 {
1135 compatible = "ti,phy-pipe3-sata";
1136 reg = <0x4A096000 0x80>, /* phy_rx */
1137 <0x4A096400 0x64>, /* phy_tx */
1138 <0x4A096800 0x40>; /* pll_ctrl */
1139 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1140 ctrl-module = <&omap_control_sata>;
1141 clocks = <&sys_clkin1>, <&sata_ref_clk>;
1142 clock-names = "sysclk", "refclk";
1143 #phy-cells = <0>;
1144 };
1145
1146 pcie1_phy: pciephy@4a094000 {
1147 compatible = "ti,phy-pipe3-pcie";
1148 reg = <0x4a094000 0x80>, /* phy_rx */
1149 <0x4a094400 0x64>; /* phy_tx */
1150 reg-names = "phy_rx", "phy_tx";
1151 ctrl-module = <&omap_control_pcie1phy>;
1152 clocks = <&dpll_pcie_ref_ck>,
1153 <&dpll_pcie_ref_m2ldo_ck>,
1154 <&optfclk_pciephy1_32khz>,
1155 <&optfclk_pciephy1_clk>,
1156 <&optfclk_pciephy1_div_clk>,
1157 <&optfclk_pciephy_div>;
1158 clock-names = "dpll_ref", "dpll_ref_m2",
1159 "wkupclk", "refclk",
1160 "div-clk", "phy-div";
1161 #phy-cells = <0>;
1162 };
1163
1164 pcie2_phy: pciephy@4a095000 {
1165 compatible = "ti,phy-pipe3-pcie";
1166 reg = <0x4a095000 0x80>, /* phy_rx */
1167 <0x4a095400 0x64>; /* phy_tx */
1168 reg-names = "phy_rx", "phy_tx";
1169 ctrl-module = <&omap_control_pcie2phy>;
1170 clocks = <&dpll_pcie_ref_ck>,
1171 <&dpll_pcie_ref_m2ldo_ck>,
1172 <&optfclk_pciephy2_32khz>,
1173 <&optfclk_pciephy2_clk>,
1174 <&optfclk_pciephy2_div_clk>,
1175 <&optfclk_pciephy_div>;
1176 clock-names = "dpll_ref", "dpll_ref_m2",
1177 "wkupclk", "refclk",
1178 "div-clk", "phy-div";
1179 #phy-cells = <0>;
1180 status = "disabled";
1181 };
1182 };
1183
1184 sata: sata@4a141100 {
1185 compatible = "snps,dwc-ahci";
1186 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1187 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1188 phys = <&sata_phy>;
1189 phy-names = "sata-phy";
1190 clocks = <&sata_ref_clk>;
1191 ti,hwmods = "sata";
1192 };
1193
1194 omap_control_pcie1phy: control-phy@0x4a003c40 {
1195 compatible = "ti,control-phy-pcie";
1196 reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1197 reg-names = "power", "control_sma", "pcie_pcs";
1198 clocks = <&sys_clkin1>;
1199 clock-names = "sysclk";
1200 };
1201
1202 omap_control_pcie2phy: control-pcie@0x4a003c44 {
1203 compatible = "ti,control-phy-pcie";
1204 reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1205 reg-names = "power", "control_sma", "pcie_pcs";
1206 clocks = <&sys_clkin1>;
1207 clock-names = "sysclk";
1208 status = "disabled";
1209 };
1210
1211 rtc: rtc@48838000 {
1212 compatible = "ti,am3352-rtc";
1213 reg = <0x48838000 0x100>;
1214 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1215 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1216 ti,hwmods = "rtcss";
1217 clocks = <&sys_32k_ck>;
1218 };
1219
1220 omap_control_usb2phy1: control-phy@4a002300 {
1221 compatible = "ti,control-phy-usb2";
1222 reg = <0x4a002300 0x4>;
1223 reg-names = "power";
1224 };
1225
1226 omap_control_usb3phy1: control-phy@4a002370 {
1227 compatible = "ti,control-phy-pipe3";
1228 reg = <0x4a002370 0x4>;
1229 reg-names = "power";
1230 };
1231
1232 omap_control_usb2phy2: control-phy@0x4a002e74 {
1233 compatible = "ti,control-phy-usb2-dra7";
1234 reg = <0x4a002e74 0x4>;
1235 reg-names = "power";
1236 };
1237
1238 /* OCP2SCP1 */
1239 ocp2scp@4a080000 {
1240 compatible = "ti,omap-ocp2scp";
1241 #address-cells = <1>;
1242 #size-cells = <1>;
1243 ranges;
1244 reg = <0x4a080000 0x20>;
1245 ti,hwmods = "ocp2scp1";
1246
1247 usb2_phy1: phy@4a084000 {
1248 compatible = "ti,omap-usb2";
1249 reg = <0x4a084000 0x400>;
1250 ctrl-module = <&omap_control_usb2phy1>;
1251 clocks = <&usb_phy1_always_on_clk32k>,
1252 <&usb_otg_ss1_refclk960m>;
1253 clock-names = "wkupclk",
1254 "refclk";
1255 #phy-cells = <0>;
1256 };
1257
1258 usb2_phy2: phy@4a085000 {
1259 compatible = "ti,omap-usb2";
1260 reg = <0x4a085000 0x400>;
1261 ctrl-module = <&omap_control_usb2phy2>;
1262 clocks = <&usb_phy2_always_on_clk32k>,
1263 <&usb_otg_ss2_refclk960m>;
1264 clock-names = "wkupclk",
1265 "refclk";
1266 #phy-cells = <0>;
1267 };
1268
1269 usb3_phy1: phy@4a084400 {
1270 compatible = "ti,omap-usb3";
1271 reg = <0x4a084400 0x80>,
1272 <0x4a084800 0x64>,
1273 <0x4a084c00 0x40>;
1274 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1275 ctrl-module = <&omap_control_usb3phy1>;
1276 clocks = <&usb_phy3_always_on_clk32k>,
1277 <&sys_clkin1>,
1278 <&usb_otg_ss1_refclk960m>;
1279 clock-names = "wkupclk",
1280 "sysclk",
1281 "refclk";
1282 #phy-cells = <0>;
1283 };
1284 };
1285
1286 omap_dwc3_1: omap_dwc3_1@48880000 {
1287 compatible = "ti,dwc3";
1288 ti,hwmods = "usb_otg_ss1";
1289 reg = <0x48880000 0x10000>;
1290 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1291 #address-cells = <1>;
1292 #size-cells = <1>;
1293 utmi-mode = <2>;
1294 ranges;
1295 usb1: usb@48890000 {
1296 compatible = "snps,dwc3";
1297 reg = <0x48890000 0x17000>;
1298 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1299 phys = <&usb2_phy1>, <&usb3_phy1>;
1300 phy-names = "usb2-phy", "usb3-phy";
1301 tx-fifo-resize;
1302 maximum-speed = "super-speed";
1303 dr_mode = "otg";
1304 snps,dis_u3_susphy_quirk;
1305 snps,dis_u2_susphy_quirk;
1306 };
1307 };
1308
1309 omap_dwc3_2: omap_dwc3_2@488c0000 {
1310 compatible = "ti,dwc3";
1311 ti,hwmods = "usb_otg_ss2";
1312 reg = <0x488c0000 0x10000>;
1313 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1314 #address-cells = <1>;
1315 #size-cells = <1>;
1316 utmi-mode = <2>;
1317 ranges;
1318 usb2: usb@488d0000 {
1319 compatible = "snps,dwc3";
1320 reg = <0x488d0000 0x17000>;
1321 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1322 phys = <&usb2_phy2>;
1323 phy-names = "usb2-phy";
1324 tx-fifo-resize;
1325 maximum-speed = "high-speed";
1326 dr_mode = "otg";
1327 snps,dis_u3_susphy_quirk;
1328 snps,dis_u2_susphy_quirk;
1329 };
1330 };
1331
1332 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1333 omap_dwc3_3: omap_dwc3_3@48900000 {
1334 compatible = "ti,dwc3";
1335 ti,hwmods = "usb_otg_ss3";
1336 reg = <0x48900000 0x10000>;
1337 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1338 #address-cells = <1>;
1339 #size-cells = <1>;
1340 utmi-mode = <2>;
1341 ranges;
1342 status = "disabled";
1343 usb3: usb@48910000 {
1344 compatible = "snps,dwc3";
1345 reg = <0x48910000 0x17000>;
1346 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1347 tx-fifo-resize;
1348 maximum-speed = "high-speed";
1349 dr_mode = "otg";
1350 snps,dis_u3_susphy_quirk;
1351 snps,dis_u2_susphy_quirk;
1352 };
1353 };
1354
1355 elm: elm@48078000 {
1356 compatible = "ti,am3352-elm";
1357 reg = <0x48078000 0xfc0>; /* device IO registers */
1358 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1359 ti,hwmods = "elm";
1360 status = "disabled";
1361 };
1362
1363 gpmc: gpmc@50000000 {
1364 compatible = "ti,am3352-gpmc";
1365 ti,hwmods = "gpmc";
1366 reg = <0x50000000 0x37c>; /* device IO registers */
1367 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1368 gpmc,num-cs = <8>;
1369 gpmc,num-waitpins = <2>;
1370 #address-cells = <2>;
1371 #size-cells = <1>;
1372 status = "disabled";
1373 };
1374
1375 atl: atl@4843c000 {
1376 compatible = "ti,dra7-atl";
1377 reg = <0x4843c000 0x3ff>;
1378 ti,hwmods = "atl";
1379 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1380 <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1381 clocks = <&atl_gfclk_mux>;
1382 clock-names = "fck";
1383 status = "disabled";
1384 };
1385
1386 crossbar_mpu: crossbar@4a002a48 {
1387 compatible = "ti,irq-crossbar";
1388 reg = <0x4a002a48 0x130>;
1389 interrupt-controller;
1390 interrupt-parent = <&wakeupgen>;
1391 #interrupt-cells = <3>;
1392 ti,max-irqs = <160>;
1393 ti,max-crossbar-sources = <MAX_SOURCES>;
1394 ti,reg-size = <2>;
1395 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1396 ti,irqs-skip = <10 133 139 140>;
1397 ti,irqs-safe-map = <0>;
1398 };
1399
1400 mac: ethernet@4a100000 {
1401 compatible = "ti,cpsw";
1402 ti,hwmods = "gmac";
1403 clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
1404 clock-names = "fck", "cpts";
1405 cpdma_channels = <8>;
1406 ale_entries = <1024>;
1407 bd_ram_size = <0x2000>;
1408 no_bd_ram = <0>;
1409 rx_descs = <64>;
1410 mac_control = <0x20>;
1411 slaves = <2>;
1412 active_slave = <0>;
1413 cpts_clock_mult = <0x80000000>;
1414 cpts_clock_shift = <29>;
1415 reg = <0x48484000 0x1000
1416 0x48485200 0x2E00>;
1417 #address-cells = <1>;
1418 #size-cells = <1>;
1419 /*
1420 * rx_thresh_pend
1421 * rx_pend
1422 * tx_pend
1423 * misc_pend
1424 */
1425 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1426 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1427 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1428 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1429 ranges;
1430 status = "disabled";
1431
1432 davinci_mdio: mdio@48485000 {
1433 compatible = "ti,davinci_mdio";
1434 #address-cells = <1>;
1435 #size-cells = <0>;
1436 ti,hwmods = "davinci_mdio";
1437 bus_freq = <1000000>;
1438 reg = <0x48485000 0x100>;
1439 };
1440
1441 cpsw_emac0: slave@48480200 {
1442 /* Filled in by U-Boot */
1443 mac-address = [ 00 00 00 00 00 00 ];
1444 };
1445
1446 cpsw_emac1: slave@48480300 {
1447 /* Filled in by U-Boot */
1448 mac-address = [ 00 00 00 00 00 00 ];
1449 };
1450
1451 phy_sel: cpsw-phy-sel@4a002554 {
1452 compatible = "ti,dra7xx-cpsw-phy-sel";
1453 reg= <0x4a002554 0x4>;
1454 reg-names = "gmii-sel";
1455 };
1456 };
1457
1458 dcan1: can@481cc000 {
1459 compatible = "ti,dra7-d_can";
1460 ti,hwmods = "dcan1";
1461 reg = <0x4ae3c000 0x2000>;
1462 syscon-raminit = <&scm_conf 0x558 0>;
1463 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1464 clocks = <&dcan1_sys_clk_mux>;
1465 status = "disabled";
1466 };
1467
1468 dcan2: can@481d0000 {
1469 compatible = "ti,dra7-d_can";
1470 ti,hwmods = "dcan2";
1471 reg = <0x48480000 0x2000>;
1472 syscon-raminit = <&scm_conf 0x558 1>;
1473 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1474 clocks = <&sys_clkin1>;
1475 status = "disabled";
1476 };
1477
1478 dss: dss@58000000 {
1479 compatible = "ti,dra7-dss";
1480 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
1481 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
1482 status = "disabled";
1483 ti,hwmods = "dss_core";
1484 /* CTRL_CORE_DSS_PLL_CONTROL */
1485 syscon-pll-ctrl = <&scm_conf 0x538>;
1486 #address-cells = <1>;
1487 #size-cells = <1>;
1488 ranges;
1489
1490 dispc@58001000 {
1491 compatible = "ti,dra7-dispc";
1492 reg = <0x58001000 0x1000>;
1493 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1494 ti,hwmods = "dss_dispc";
1495 clocks = <&dss_dss_clk>;
1496 clock-names = "fck";
1497 /* CTRL_CORE_SMA_SW_1 */
1498 syscon-pol = <&scm_conf 0x534>;
1499 };
1500
1501 hdmi: encoder@58060000 {
1502 compatible = "ti,dra7-hdmi";
1503 reg = <0x58040000 0x200>,
1504 <0x58040200 0x80>,
1505 <0x58040300 0x80>,
1506 <0x58060000 0x19000>;
1507 reg-names = "wp", "pll", "phy", "core";
1508 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1509 status = "disabled";
1510 ti,hwmods = "dss_hdmi";
1511 clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
1512 clock-names = "fck", "sys_clk";
1513 };
1514 };
1515 };
1516
1517 thermal_zones: thermal-zones {
1518 #include "omap4-cpu-thermal.dtsi"
1519 #include "omap5-gpu-thermal.dtsi"
1520 #include "omap5-core-thermal.dtsi"
1521 };
1522
1523};
1524
1525&cpu_thermal {
1526 polling-delay = <500>; /* milliseconds */
1527};
1528
1529/include/ "dra7xx-clocks.dtsi"