blob: 4cdc2ecd1d2390f8aabd5ad52be122d8ef17696e [file] [log] [blame]
Michal Simek4b066a12018-08-22 14:55:27 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2014 - 2018 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
5 */
6
Algapally Santosh Sagar3c351b22023-01-19 22:36:16 -07007#include <command.h>
Michal Simek4b066a12018-08-22 14:55:27 +02008#include <common.h>
Simon Glassafb02152019-12-28 10:45:01 -07009#include <cpu_func.h>
Simon Glassed38aef2020-05-10 11:40:03 -060010#include <env.h>
Michal Simek4b066a12018-08-22 14:55:27 +020011#include <fdtdec.h>
Simon Glassa7b51302019-11-14 12:57:46 -070012#include <init.h>
Ashok Reddy Somafb6b3cd2021-02-23 08:07:46 -070013#include <env_internal.h>
Simon Glass0f2af882020-05-10 11:40:05 -060014#include <log.h>
Michal Simek4b066a12018-08-22 14:55:27 +020015#include <malloc.h>
Simon Glass495a5dc2019-11-14 12:57:30 -070016#include <time.h>
Simon Glass274e0b02020-05-10 11:39:56 -060017#include <asm/cache.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060018#include <asm/global_data.h>
Michal Simek4b066a12018-08-22 14:55:27 +020019#include <asm/io.h>
20#include <asm/arch/hardware.h>
Michal Simek21eb5cc2019-04-29 09:39:09 -070021#include <asm/arch/sys_proto.h>
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +053022#include <dm/device.h>
23#include <dm/uclass.h>
Siva Durga Prasad Paladugub7398972019-08-05 15:54:59 +053024#include <versalpl.h>
Michal Simek705d44a2020-03-31 12:39:37 +020025#include "../common/board.h"
Michal Simek4b066a12018-08-22 14:55:27 +020026
27DECLARE_GLOBAL_DATA_PTR;
28
Siva Durga Prasad Paladugub7398972019-08-05 15:54:59 +053029#if defined(CONFIG_FPGA_VERSALPL)
Oleksandr Suvorovdae95a42022-07-22 17:16:04 +030030static xilinx_desc versalpl = {
31 xilinx_versal, csu_dma, 1, &versal_op, 0, &versal_op, NULL,
32 FPGA_LEGACY
33};
Siva Durga Prasad Paladugub7398972019-08-05 15:54:59 +053034#endif
35
Michal Simek4b066a12018-08-22 14:55:27 +020036int board_init(void)
37{
38 printf("EL Level:\tEL%d\n", current_el());
39
Siva Durga Prasad Paladugub7398972019-08-05 15:54:59 +053040#if defined(CONFIG_FPGA_VERSALPL)
41 fpga_init();
42 fpga_add(fpga_xilinx, &versalpl);
43#endif
44
Michal Simek394ee242020-08-03 13:01:45 +020045 if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
46 xilinx_read_eeprom();
47
Michal Simek4b066a12018-08-22 14:55:27 +020048 return 0;
49}
50
51int board_early_init_r(void)
52{
Michal Simek19f6c972019-01-28 11:08:00 +010053 u32 val;
Michal Simek4b066a12018-08-22 14:55:27 +020054
Michal Simek19f6c972019-01-28 11:08:00 +010055 if (current_el() != 3)
56 return 0;
Michal Simek4b066a12018-08-22 14:55:27 +020057
Michal Simekf56f7d12019-01-28 11:12:41 +010058 debug("iou_switch ctrl div0 %x\n",
59 readl(&crlapb_base->iou_switch_ctrl));
60
Michal Simek19f6c972019-01-28 11:08:00 +010061 writel(IOU_SWITCH_CTRL_CLKACT_BIT |
Michal Simekf56f7d12019-01-28 11:12:41 +010062 (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
Michal Simek19f6c972019-01-28 11:08:00 +010063 &crlapb_base->iou_switch_ctrl);
Michal Simek4b066a12018-08-22 14:55:27 +020064
Michal Simek19f6c972019-01-28 11:08:00 +010065 /* Global timer init - Program time stamp reference clk */
66 val = readl(&crlapb_base->timestamp_ref_ctrl);
67 val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
68 writel(val, &crlapb_base->timestamp_ref_ctrl);
Michal Simek4b066a12018-08-22 14:55:27 +020069
Michal Simek19f6c972019-01-28 11:08:00 +010070 debug("ref ctrl 0x%x\n",
71 readl(&crlapb_base->timestamp_ref_ctrl));
Michal Simek4b066a12018-08-22 14:55:27 +020072
Michal Simek19f6c972019-01-28 11:08:00 +010073 /* Clear reset of timestamp reg */
74 writel(0, &crlapb_base->rst_timestamp);
Michal Simek4b066a12018-08-22 14:55:27 +020075
Michal Simek19f6c972019-01-28 11:08:00 +010076 /*
77 * Program freq register in System counter and
78 * enable system counter.
79 */
Peng Fan4b3a1822022-04-13 17:47:17 +080080 writel(CONFIG_COUNTER_FREQUENCY,
Michal Simek19f6c972019-01-28 11:08:00 +010081 &iou_scntr_secure->base_frequency_id_register);
Michal Simek4b066a12018-08-22 14:55:27 +020082
Michal Simek19f6c972019-01-28 11:08:00 +010083 debug("counter val 0x%x\n",
84 readl(&iou_scntr_secure->base_frequency_id_register));
85
86 writel(IOU_SCNTRS_CONTROL_EN,
87 &iou_scntr_secure->counter_control_register);
Michal Simek4b066a12018-08-22 14:55:27 +020088
Michal Simek19f6c972019-01-28 11:08:00 +010089 debug("scntrs control 0x%x\n",
90 readl(&iou_scntr_secure->counter_control_register));
91 debug("timer 0x%llx\n", get_ticks());
92 debug("timer 0x%llx\n", get_ticks());
Michal Simek4b066a12018-08-22 14:55:27 +020093
94 return 0;
95}
96
Ashok Reddy Soma6c191052022-05-05 23:53:45 -060097unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
98 char *const argv[])
99{
100 int ret = 0;
101
102 if (current_el() > 1) {
103 smp_kick_all_cpus();
104 dcache_disable();
105 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
106 ES_TO_AARCH64);
107 } else {
108 printf("FAIL: current EL is not above EL1\n");
109 ret = EINVAL;
110 }
111 return ret;
112}
113
Michal Simek9c91e612020-04-08 11:04:41 +0200114static u8 versal_get_bootmode(void)
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530115{
Michal Simek9c91e612020-04-08 11:04:41 +0200116 u8 bootmode;
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530117 u32 reg = 0;
Michal Simek9c91e612020-04-08 11:04:41 +0200118
119 reg = readl(&crp_base->boot_mode_usr);
120
121 if (reg >> BOOT_MODE_ALT_SHIFT)
122 reg >>= BOOT_MODE_ALT_SHIFT;
123
124 bootmode = reg & BOOT_MODES_MASK;
125
126 return bootmode;
127}
128
129int board_late_init(void)
130{
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530131 u8 bootmode;
132 struct udevice *dev;
133 int bootseq = -1;
134 int bootseq_len = 0;
135 int env_targets_len = 0;
136 const char *mode;
137 char *new_targets;
138 char *env_targets;
139
140 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
141 debug("Saved variables - Skipping\n");
142 return 0;
143 }
144
Michal Simekbab07b62020-07-28 12:45:47 +0200145 if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
146 return 0;
147
Michal Simek9c91e612020-04-08 11:04:41 +0200148 bootmode = versal_get_bootmode();
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530149
150 puts("Bootmode: ");
151 switch (bootmode) {
T Karthik Reddyfacca9a2019-07-11 16:07:57 +0530152 case USB_MODE:
153 puts("USB_MODE\n");
T Karthik Reddy1104faf2021-03-30 23:24:57 -0600154 mode = "usb_dfu0 usb_dfu1";
T Karthik Reddyfacca9a2019-07-11 16:07:57 +0530155 break;
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530156 case JTAG_MODE:
157 puts("JTAG_MODE\n");
Siva Durga Prasad Paladugu00784e02019-06-25 17:13:14 +0530158 mode = "jtag pxe dhcp";
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530159 break;
160 case QSPI_MODE_24BIT:
161 puts("QSPI_MODE_24\n");
162 mode = "xspi0";
163 break;
164 case QSPI_MODE_32BIT:
165 puts("QSPI_MODE_32\n");
166 mode = "xspi0";
167 break;
168 case OSPI_MODE:
169 puts("OSPI_MODE\n");
170 mode = "xspi0";
171 break;
172 case EMMC_MODE:
173 puts("EMMC_MODE\n");
T Karthik Reddybc2b9642019-12-16 04:44:26 -0700174 if (uclass_get_device_by_name(UCLASS_MMC,
T Karthik Reddya12445f2021-11-18 12:57:20 +0100175 "mmc@f1050000", &dev) &&
176 uclass_get_device_by_name(UCLASS_MMC,
T Karthik Reddybc2b9642019-12-16 04:44:26 -0700177 "sdhci@f1050000", &dev)) {
178 puts("Boot from EMMC but without SD1 enabled!\n");
179 return -1;
180 }
Simon Glass75e534b2020-12-16 21:20:07 -0700181 debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
T Karthik Reddybc2b9642019-12-16 04:44:26 -0700182 mode = "mmc";
Simon Glass75e534b2020-12-16 21:20:07 -0700183 bootseq = dev_seq(dev);
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530184 break;
185 case SD_MODE:
186 puts("SD_MODE\n");
187 if (uclass_get_device_by_name(UCLASS_MMC,
T Karthik Reddya12445f2021-11-18 12:57:20 +0100188 "mmc@f1040000", &dev) &&
189 uclass_get_device_by_name(UCLASS_MMC,
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530190 "sdhci@f1040000", &dev)) {
191 puts("Boot from SD0 but without SD0 enabled!\n");
192 return -1;
193 }
Simon Glass75e534b2020-12-16 21:20:07 -0700194 debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530195
196 mode = "mmc";
Simon Glass75e534b2020-12-16 21:20:07 -0700197 bootseq = dev_seq(dev);
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530198 break;
199 case SD1_LSHFT_MODE:
200 puts("LVL_SHFT_");
201 /* fall through */
202 case SD_MODE1:
203 puts("SD_MODE1\n");
204 if (uclass_get_device_by_name(UCLASS_MMC,
T Karthik Reddya12445f2021-11-18 12:57:20 +0100205 "mmc@f1050000", &dev) &&
206 uclass_get_device_by_name(UCLASS_MMC,
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530207 "sdhci@f1050000", &dev)) {
208 puts("Boot from SD1 but without SD1 enabled!\n");
209 return -1;
210 }
Simon Glass75e534b2020-12-16 21:20:07 -0700211 debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530212
213 mode = "mmc";
Simon Glass75e534b2020-12-16 21:20:07 -0700214 bootseq = dev_seq(dev);
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530215 break;
216 default:
217 mode = "";
218 printf("Invalid Boot Mode:0x%x\n", bootmode);
219 break;
220 }
221
222 if (bootseq >= 0) {
223 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
224 debug("Bootseq len: %x\n", bootseq_len);
225 }
226
227 /*
228 * One terminating char + one byte for space between mode
229 * and default boot_targets
230 */
231 env_targets = env_get("boot_targets");
232 if (env_targets)
233 env_targets_len = strlen(env_targets);
234
235 new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
236 bootseq_len);
237 if (!new_targets)
238 return -ENOMEM;
239
240 if (bootseq >= 0)
241 sprintf(new_targets, "%s%x %s", mode, bootseq,
242 env_targets ? env_targets : "");
243 else
244 sprintf(new_targets, "%s %s", mode,
245 env_targets ? env_targets : "");
246
247 env_set("boot_targets", new_targets);
248
Michal Simek705d44a2020-03-31 12:39:37 +0200249 return board_late_init_xilinx();
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530250}
251
Michal Simek4b066a12018-08-22 14:55:27 +0200252int dram_init_banksize(void)
253{
Michal Simek21eb5cc2019-04-29 09:39:09 -0700254 int ret;
255
256 ret = fdtdec_setup_memory_banksize();
257 if (ret)
258 return ret;
259
260 mem_map_fill();
Michal Simek4b066a12018-08-22 14:55:27 +0200261
262 return 0;
263}
264
265int dram_init(void)
266{
Michal Simek9134d4c2020-07-10 12:42:09 +0200267 if (fdtdec_setup_mem_size_base_lowest() != 0)
Michal Simek4b066a12018-08-22 14:55:27 +0200268 return -EINVAL;
269
270 return 0;
271}
272
Harald Seiler6f14d5f2020-12-15 16:47:52 +0100273void reset_cpu(void)
Michal Simek4b066a12018-08-22 14:55:27 +0200274{
275}
Ashok Reddy Somafb6b3cd2021-02-23 08:07:46 -0700276
277enum env_location env_get_location(enum env_operation op, int prio)
278{
279 u32 bootmode = versal_get_bootmode();
280
281 if (prio)
282 return ENVL_UNKNOWN;
283
284 switch (bootmode) {
285 case EMMC_MODE:
286 case SD_MODE:
287 case SD1_LSHFT_MODE:
288 case SD_MODE1:
289 if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
290 return ENVL_FAT;
291 if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
292 return ENVL_EXT4;
T Karthik Reddy6f8b2052021-11-24 12:16:55 +0100293 return ENVL_NOWHERE;
Ashok Reddy Somafb6b3cd2021-02-23 08:07:46 -0700294 case OSPI_MODE:
295 case QSPI_MODE_24BIT:
296 case QSPI_MODE_32BIT:
297 if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
298 return ENVL_SPI_FLASH;
T Karthik Reddy6f8b2052021-11-24 12:16:55 +0100299 return ENVL_NOWHERE;
Ashok Reddy Somafb6b3cd2021-02-23 08:07:46 -0700300 case JTAG_MODE:
301 default:
302 return ENVL_NOWHERE;
303 }
304}