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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Andy Fleming71706df2007-04-23 02:54:25 -05002/*
3 * Copyright 2007 Freescale Semiconductor.
Andy Fleming71706df2007-04-23 02:54:25 -05004 */
5
6#include <common.h>
Anton Vorontsov734b4422007-10-22 18:12:46 +04007#include <asm/io.h>
8
Andy Fleming71706df2007-04-23 02:54:25 -05009#include "bcsr.h"
10
Kim Phillips402673f2012-10-29 13:34:38 +000011void enable_8568mds_duart(void)
Andy Fleming71706df2007-04-23 02:54:25 -050012{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020013 volatile uint* duart_mux = (uint *)(CONFIG_SYS_CCSRBAR + 0xe0060);
14 volatile uint* devices = (uint *)(CONFIG_SYS_CCSRBAR + 0xe0070);
15 volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
Andy Fleming71706df2007-04-23 02:54:25 -050016
17 *duart_mux = 0x80000000; /* Set the mux to Duart on PMUXCR */
18 *devices = 0; /* Enable all peripheral devices */
19 bcsr[5] |= 0x01; /* Enable Duart in BCSR*/
20}
21
Kim Phillips402673f2012-10-29 13:34:38 +000022void enable_8568mds_flash_write(void)
Andy Fleming71706df2007-04-23 02:54:25 -050023{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020024 volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
Andy Fleming71706df2007-04-23 02:54:25 -050025
26 bcsr[9] |= 0x01;
27}
28
Kim Phillips402673f2012-10-29 13:34:38 +000029void disable_8568mds_flash_write(void)
Andy Fleming71706df2007-04-23 02:54:25 -050030{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020031 volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
Andy Fleming71706df2007-04-23 02:54:25 -050032
33 bcsr[9] &= ~(0x01);
34}
Andy Flemingee0e9172007-08-14 00:14:25 -050035
Kim Phillips402673f2012-10-29 13:34:38 +000036void enable_8568mds_qe_mdio(void)
Andy Flemingee0e9172007-08-14 00:14:25 -050037{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020038 u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
Andy Flemingee0e9172007-08-14 00:14:25 -050039
40 bcsr[7] |= 0x01;
41}
Anton Vorontsov734b4422007-10-22 18:12:46 +040042
43#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
44void reset_8568mds_uccs(void)
45{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020046 volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
Anton Vorontsov734b4422007-10-22 18:12:46 +040047
48 /* Turn off UCC1 & UCC2 */
49 out_8(&bcsr[8], in_8(&bcsr[8]) & ~BCSR_UCC1_GETH_EN);
50 out_8(&bcsr[9], in_8(&bcsr[9]) & ~BCSR_UCC2_GETH_EN);
51
52 /* Mode is RGMII, all bits clear */
53 out_8(&bcsr[11], in_8(&bcsr[11]) & ~(BCSR_UCC1_MODE_MSK |
54 BCSR_UCC2_MODE_MSK));
55
56 /* Turn UCC1 & UCC2 on */
57 out_8(&bcsr[8], in_8(&bcsr[8]) | BCSR_UCC1_GETH_EN);
58 out_8(&bcsr[9], in_8(&bcsr[9]) | BCSR_UCC2_GETH_EN);
59}
60#endif