blob: c0086dda9b9e6f15c1f8799569f4813c2eb3b3ae [file] [log] [blame]
wdenk7eaacc52003-08-29 22:00:43 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Alex Zuepke <azu@sysgo.de>
9 *
10 * (C) Copyright 2002
11 * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
12 *
13 * See file CREDITS for list of people who contributed to this
14 * project.
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * MA 02111-1307 USA
30 */
31
32#include <common.h>
33#include <arm925t.h>
34#include <configs/omap1510.h>
35
36#include <asm/proc-armv/ptrace.h>
37
38extern void reset_cpu(ulong addr);
39#define TIMER_LOAD_VAL 0xffffffff
40
41/* macro to read the 32 bit timer */
42#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8))
43
44#ifdef CONFIG_USE_IRQ
45/* enable IRQ interrupts */
46void enable_interrupts (void)
47{
48 unsigned long temp;
49 __asm__ __volatile__("mrs %0, cpsr\n"
50 "bic %0, %0, #0x80\n"
51 "msr cpsr_c, %0"
52 : "=r" (temp)
53 : "memory");
54}
55
56/*
57 * disable IRQ/FIQ interrupts
58 * returns true if interrupts had been enabled before we disabled them
59 */
60int disable_interrupts (void)
61{
62 unsigned long old,temp;
63 __asm__ __volatile__("mrs %0, cpsr\n"
64 "orr %1, %0, #0xc0\n"
65 "msr cpsr_c, %1"
66 : "=r" (old), "=r" (temp)
67 : "memory");
68 return (old & 0x80) == 0;
69}
70#else
71void enable_interrupts (void)
72{
73 return;
74}
75int disable_interrupts (void)
76{
77 return 0;
78}
79#endif
80
81
82
83void bad_mode (void)
84{
85 panic ("Resetting CPU ...\n");
86 reset_cpu (0);
87}
88
89void show_regs (struct pt_regs *regs)
90{
91 unsigned long flags;
92 const char *processor_modes[] = {
93 "USER_26", "FIQ_26", "IRQ_26", "SVC_26",
94 "UK4_26", "UK5_26", "UK6_26", "UK7_26",
95 "UK8_26", "UK9_26", "UK10_26", "UK11_26",
96 "UK12_26", "UK13_26", "UK14_26", "UK15_26",
97 "USER_32", "FIQ_32", "IRQ_32", "SVC_32",
98 "UK4_32", "UK5_32", "UK6_32", "ABT_32",
99 "UK8_32", "UK9_32", "UK10_32", "UND_32",
100 "UK12_32", "UK13_32", "UK14_32", "SYS_32",
101 };
102
103 flags = condition_codes (regs);
104
105 printf ("pc : [<%08lx>] lr : [<%08lx>]\n"
106 "sp : %08lx ip : %08lx fp : %08lx\n",
107 instruction_pointer (regs),
108 regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
109 printf ("r10: %08lx r9 : %08lx r8 : %08lx\n",
110 regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
111 printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
112 regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
113 printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
114 regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
115 printf ("Flags: %c%c%c%c",
116 flags & CC_N_BIT ? 'N' : 'n',
117 flags & CC_Z_BIT ? 'Z' : 'z',
118 flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
119 printf (" IRQs %s FIQs %s Mode %s%s\n",
120 interrupts_enabled (regs) ? "on" : "off",
121 fast_interrupts_enabled (regs) ? "on" : "off",
122 processor_modes[processor_mode (regs)],
123 thumb_mode (regs) ? " (T)" : "");
124}
125
126void do_undefined_instruction (struct pt_regs *pt_regs)
127{
128 printf ("undefined instruction\n");
129 show_regs (pt_regs);
130 bad_mode ();
131}
132
133void do_software_interrupt (struct pt_regs *pt_regs)
134{
135 printf ("software interrupt\n");
136 show_regs (pt_regs);
137 bad_mode ();
138}
139
140void do_prefetch_abort (struct pt_regs *pt_regs)
141{
142 printf ("prefetch abort\n");
143 show_regs (pt_regs);
144 bad_mode ();
145}
146
147void do_data_abort (struct pt_regs *pt_regs)
148{
149 printf ("data abort\n");
150 show_regs (pt_regs);
151 bad_mode ();
152}
153
154void do_not_used (struct pt_regs *pt_regs)
155{
156 printf ("not used\n");
157 show_regs (pt_regs);
158 bad_mode ();
159}
160
161void do_fiq (struct pt_regs *pt_regs)
162{
163 printf ("fast interrupt request\n");
164 show_regs (pt_regs);
165 bad_mode ();
166}
167
168void do_irq (struct pt_regs *pt_regs)
169{
170 printf ("interrupt request\n");
171 show_regs (pt_regs);
172 bad_mode ();
173}
174
175static ulong timestamp;
176static ulong lastdec;
177
178/* nothing really to do with interrupts, just starts up a counter. */
179int interrupt_init (void)
180{
181 int32_t val;
182
183 *((int32_t *) (CFG_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
184 val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE |
185 (CFG_PVT << MPUTIM_PTV_BIT);
186 *((int32_t *) (CFG_TIMERBASE + CNTL_TIMER)) = val;
187 return (0);
188}
189
190/*
191 * timer without interrupts
192 */
193
194void reset_timer (void)
195{
196 reset_timer_masked ();
197}
198
199ulong get_timer (ulong base)
200{
201 return get_timer_masked () - base;
202}
203
204void set_timer (ulong t)
205{
206 timestamp = t;
207}
208
209/* very rough timer... */
210void udelay (unsigned long usec)
211{
212#ifdef CONFIG_INNOVATOROMAP1610
213#define LOOPS_PER_MSEC 100 /* tuned on omap1610 */
214 volatile int i, time_remaining = LOOPS_PER_MSEC * usec;
215
216 for (i = time_remaining; i > 0; i--) {
217 }
218#else
219
220 ulong tmo;
221 tmo = usec / 1000;
222 tmo *= CFG_HZ;
223 tmo /= 1000;
224 tmo += get_timer (0);
225 while (get_timer_masked () < tmo)
226 /*NOP*/;
227#endif
228}
229
230void reset_timer_masked (void)
231{
232 /* reset time */
233 lastdec = READ_TIMER;
234 timestamp = 0;
235}
236
237ulong get_timer_masked (void)
238{
239 ulong now = READ_TIMER; /* current tick value */
240
241 if (lastdec >= now) { /* did I roll (rem decrementer) */
242 /* normal mode */
243 /* record amount of time since last check */
244 timestamp += lastdec - now;
245 } else {
246 /* we have an overflow ... */
247 timestamp += lastdec + TIMER_LOAD_VAL - now;
248 }
249 lastdec = now;
250
251 return timestamp;
252}
253
254void udelay_masked (unsigned long usec)
255{
256#ifdef CONFIG_INNOVATOROMAP1610
257 #define LOOPS_PER_MSEC 100 /* tuned on omap1610 */
258 volatile int i, time_remaining = LOOPS_PER_MSEC*usec;
259 for (i=time_remaining; i>0; i--) { }
260#else
261
262 ulong tmo;
263
264 tmo = usec / 1000;
265 tmo *= CFG_HZ;
266 tmo /= 1000;
267
268 reset_timer_masked ();
269
270 while (get_timer_masked () < tmo)
271 /*NOP*/;
272#endif
273}
274
275/*
276 * This function is derived from PowerPC code (read timebase as long long).
277 * On ARM it just returns the timer value.
278 */
279unsigned long long get_ticks(void)
280{
281 return get_timer(0);
282}
283
284/*
285 * This function is derived from PowerPC code (timebase clock frequency).
286 * On ARM it returns the number of timer ticks per second.
287 */
288ulong get_tbclk (void)
289{
290 ulong tbclk;
291 tbclk = CFG_HZ;
292 return tbclk;
293}