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git01.mediatek.com / filogic / uboot / bce9acf89ec22bea72b18d70d71b0f64cf6e04e1 / . / arch / arm / dts / k3-j721s2.dtsi
blob: fe5234c40f6ce891b82243afaf3cccd8f077a29f [file] [log] [blame]
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for J721S2 SoC Family
4 *
5 * TRM (SPRUJ28 – NOVEMBER 2021) : http://www.ti.com/lit/pdf/spruj28
6 *
7 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
8 *
9 */
10
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/pinctrl/k3.h>
14#include <dt-bindings/soc/ti,sci_pm_domain.h>
15
16/ {
17
18 model = "Texas Instruments K3 J721S2 SoC";
19 compatible = "ti,j721s2";
20 interrupt-parent = <&gic500>;
21 #address-cells = <2>;
22 #size-cells = <2>;
23
24 chosen { };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29 cpu-map {
30 cluster0: cluster0 {
31 core0 {
32 cpu = <&cpu0>;
33 };
34
35 core1 {
36 cpu = <&cpu1>;
37 };
38 };
39 };
40
41 cpu0: cpu@0 {
42 compatible = "arm,cortex-a72";
43 reg = <0x000>;
44 device_type = "cpu";
45 enable-method = "psci";
46 i-cache-size = <0xc000>;
47 i-cache-line-size = <64>;
48 i-cache-sets = <256>;
49 d-cache-size = <0x8000>;
50 d-cache-line-size = <64>;
51 d-cache-sets = <256>;
52 next-level-cache = <&L2_0>;
53 };
54
55 cpu1: cpu@1 {
56 compatible = "arm,cortex-a72";
57 reg = <0x001>;
58 device_type = "cpu";
59 enable-method = "psci";
60 i-cache-size = <0xc000>;
61 i-cache-line-size = <64>;
62 i-cache-sets = <256>;
63 d-cache-size = <0x8000>;
64 d-cache-line-size = <64>;
65 d-cache-sets = <256>;
66 next-level-cache = <&L2_0>;
67 };
68 };
69
70 L2_0: l2-cache0 {
71 compatible = "cache";
72 cache-level = <2>;
73 cache-size = <0x100000>;
74 cache-line-size = <64>;
75 cache-sets = <1024>;
76 next-level-cache = <&msmc_l3>;
77 };
78
79 msmc_l3: l3-cache0 {
80 compatible = "cache";
81 cache-level = <3>;
82 };
83
84 firmware {
85 optee {
86 compatible = "linaro,optee-tz";
87 method = "smc";
88 };
89
90 psci: psci {
91 compatible = "arm,psci-1.0";
92 method = "smc";
93 };
94 };
95
96 a72_timer0: timer-cl0-cpu0 {
97 compatible = "arm,armv8-timer";
98 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
99 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
100 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
101 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
102
103 };
104
105 pmu: pmu {
106 compatible = "arm,cortex-a72-pmu";
107 /* Recommendation from GIC500 TRM Table A.3 */
108 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
109 };
110
111 cbass_main: bus@100000 {
112 compatible = "simple-bus";
113 #address-cells = <2>;
114 #size-cells = <2>;
115 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
116 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
117 <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
118 <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe Core*/
119 <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
120 <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */
121 <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */
122 <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */
123 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
124 <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
125 <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
126
127 /* MCUSS_WKUP Range */
128 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
129 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
130 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
131 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
132 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
133 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
134 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
135 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
136 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
137 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
138 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
139 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
140 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
141
142 cbass_mcu_wakeup: bus@28380000 {
143 compatible = "simple-bus";
144 #address-cells = <2>;
145 #size-cells = <2>;
146 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
147 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
148 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
149 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
150 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
151 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
152 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
153 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
154 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
155 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
156 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
157 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
158 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
159
160 };
161
162 };
163};
164
165/* Now include peripherals from each bus segment */
166#include "k3-j721s2-main.dtsi"
167#include "k3-j721s2-mcu-wakeup.dtsi"