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git01.mediatek.com / filogic / uboot / bce9acf89ec22bea72b18d70d71b0f64cf6e04e1 / . / arch / arm / dts / imx8mn-evk.dtsi
blob: 416fadb22b1a86b7eed1aec4ca73193f69654772 [file] [log] [blame]
Peng Fancdc90f32020-12-27 09:37:06 +0800[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/usb/pd.h>
7#include "imx8mn.dtsi"
8
9/ {
10 chosen {
11 stdout-path = &uart2;
12 };
13
14 gpio-leds {
15 compatible = "gpio-leds";
16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_gpio_led>;
18
19 status {
20 label = "yellow:status";
21 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
22 default-state = "on";
23 };
24 };
25
26 memory@40000000 {
27 device_type = "memory";
28 reg = <0x0 0x40000000 0 0x80000000>;
29 };
30
31 reg_usdhc2_vmmc: regulator-usdhc2 {
32 compatible = "regulator-fixed";
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
35 regulator-name = "VSD_3V3";
36 regulator-min-microvolt = <3300000>;
37 regulator-max-microvolt = <3300000>;
38 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
39 enable-active-high;
40 };
41
42 ir-receiver {
43 compatible = "gpio-ir-receiver";
44 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_ir>;
47 linux,autosuspend-period = <125>;
48 };
49};
50
51&fec1 {
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_fec1>;
54 phy-mode = "rgmii-id";
55 phy-handle = <&ethphy0>;
Marek Vasutf87338f2022-02-19 17:13:54 +0100[diff] [blame]56 phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
Peng Fancdc90f32020-12-27 09:37:06 +0800[diff] [blame]57 fsl,magic-packet;
58 status = "okay";
59
60 mdio {
61 #address-cells = <1>;
62 #size-cells = <0>;
63
64 ethphy0: ethernet-phy@0 {
65 compatible = "ethernet-phy-ieee802.3-c22";
66 reg = <0>;
67 };
68 };
69};
70
71&i2c1 {
72 clock-frequency = <400000>;
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_i2c1>;
75 status = "okay";
76};
77
78&i2c2 {
79 clock-frequency = <400000>;
80 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_i2c2>;
82 status = "okay";
83
84 ptn5110: tcpc@50 {
85 compatible = "nxp,ptn5110";
86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_typec1>;
88 reg = <0x50>;
89 interrupt-parent = <&gpio2>;
90 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
91 status = "okay";
92
93 port {
94 typec1_dr_sw: endpoint {
95 remote-endpoint = <&usb1_drd_sw>;
96 };
97 };
98
99 typec1_con: connector {
100 compatible = "usb-c-connector";
101 label = "USB-C";
102 power-role = "dual";
103 data-role = "dual";
104 try-power-role = "sink";
105 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
106 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
107 PDO_VAR(5000, 20000, 3000)>;
108 op-sink-microwatt = <15000000>;
109 self-powered;
110 };
111 };
112};
113
114&i2c3 {
115 clock-frequency = <400000>;
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_i2c3>;
118 status = "okay";
119
120 pca6416: gpio@20 {
121 compatible = "ti,tca6416";
122 reg = <0x20>;
123 gpio-controller;
124 #gpio-cells = <2>;
125 };
126};
127
128&snvs_pwrkey {
129 status = "okay";
130};
131
132&uart2 { /* console */
133 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_uart2>;
135 status = "okay";
136};
137
138&usbotg1 {
139 dr_mode = "otg";
140 hnp-disable;
141 srp-disable;
142 adp-disable;
143 usb-role-switch;
144 samsung,picophy-pre-emp-curr-control = <3>;
145 samsung,picophy-dc-vol-level-adjust = <7>;
146 status = "okay";
147
148 port {
149 usb1_drd_sw: endpoint {
150 remote-endpoint = <&typec1_dr_sw>;
151 };
152 };
153};
154
155&usdhc2 {
156 assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
157 assigned-clock-rates = <200000000>;
158 pinctrl-names = "default", "state_100mhz", "state_200mhz";
159 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
160 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
161 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
162 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
163 bus-width = <4>;
164 vmmc-supply = <&reg_usdhc2_vmmc>;
165 status = "okay";
166};
167
168&usdhc3 {
169 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
170 assigned-clock-rates = <400000000>;
171 pinctrl-names = "default", "state_100mhz", "state_200mhz";
172 pinctrl-0 = <&pinctrl_usdhc3>;
173 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
174 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
175 bus-width = <8>;
176 non-removable;
177 status = "okay";
178};
179
180&wdog1 {
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_wdog>;
183 fsl,ext-reset-output;
184 status = "okay";
185};
186
187&iomuxc {
188 pinctrl_fec1: fec1grp {
189 fsl,pins = <
190 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
191 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
192 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
193 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
194 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
195 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
196 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
197 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
198 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
199 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
200 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
201 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
202 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
203 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
204 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
205 >;
206 };
207
208 pinctrl_gpio_led: gpioledgrp {
209 fsl,pins = <
210 MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
211 >;
212 };
213
214 pinctrl_ir: irgrp {
215 fsl,pins = <
216 MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f
217 >;
218 };
219
220 pinctrl_i2c1: i2c1grp {
221 fsl,pins = <
222 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
223 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
224 >;
225 };
226
227 pinctrl_i2c2: i2c2grp {
228 fsl,pins = <
229 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
230 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
231 >;
232 };
233
234 pinctrl_i2c3: i2c3grp {
235 fsl,pins = <
236 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
237 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
238 >;
239 };
240
241 pinctrl_pmic: pmicirqgrp {
242 fsl,pins = <
243 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
244 >;
245 };
246
247 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
248 fsl,pins = <
249 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
250 >;
251 };
252
253 pinctrl_typec1: typec1grp {
254 fsl,pins = <
255 MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
256 >;
257 };
258
259 pinctrl_uart2: uart2grp {
260 fsl,pins = <
261 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
262 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
263 >;
264 };
265
266 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
267 fsl,pins = <
268 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
269 >;
270 };
271
272 pinctrl_usdhc2: usdhc2grp {
273 fsl,pins = <
274 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
275 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
276 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
277 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
278 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
279 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
280 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
281 >;
282 };
283
284 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
285 fsl,pins = <
286 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
287 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
288 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
289 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
290 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
291 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
292 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
293 >;
294 };
295
296 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
297 fsl,pins = <
298 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
299 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
300 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
301 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
302 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
303 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
304 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
305 >;
306 };
307
308 pinctrl_usdhc3: usdhc3grp {
309 fsl,pins = <
310 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
311 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
312 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
313 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
314 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
315 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
316 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
317 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
318 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
319 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
320 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
321 >;
322 };
323
324 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
325 fsl,pins = <
326 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
327 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
328 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
329 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
330 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
331 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
332 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
333 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
334 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
335 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
336 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
337 >;
338 };
339
340 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
341 fsl,pins = <
342 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
343 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
344 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
345 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
346 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
347 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
348 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
349 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
350 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
351 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
352 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
353 >;
354 };
355
356 pinctrl_wdog: wdoggrp {
357 fsl,pins = <
358 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
359 >;
360 };
361};