| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| Tom Warren | c47e717 | 2013-01-28 13:32:07 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. |
| Tom Warren | c47e717 | 2013-01-28 13:32:07 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef _TEGRA114_H_ |
| 7 | #define _TEGRA114_H_ |
| 8 | |
| 9 | #define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */ |
| Tom Warren | fbef355 | 2013-04-01 15:48:54 -0700 | [diff] [blame] | 10 | #define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ |
| Marcel Ziswiler | c5ecf27 | 2014-10-10 23:32:32 +0200 | [diff] [blame] | 11 | #define NV_PA_MC_BASE 0x70019000 |
| Tom Warren | c47e717 | 2013-01-28 13:32:07 +0000 | [diff] [blame] | 12 | |
| 13 | #include <asm/arch-tegra/tegra.h> |
| 14 | |
| 15 | #define BCT_ODMDATA_OFFSET 1752 /* offset to ODMDATA word */ |
| 16 | |
| 17 | #undef NVBOOTINFOTABLE_BCTSIZE |
| 18 | #undef NVBOOTINFOTABLE_BCTPTR |
| 19 | #define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */ |
| 20 | #define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */ |
| 21 | |
| 22 | #define MAX_NUM_CPU 4 |
| 23 | |
| 24 | #endif /* TEGRA114_H */ |