blob: 4503cf3f6d0d0312c0bc6161a9b5ef6fd4f63759 [file] [log] [blame]
Masami Hiramatsu7c741272021-06-04 18:45:10 +09001/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2016-2017 Socionext Inc.
4 */
5#ifndef __CONFIG_H
6#define __CONFIG_H
7
8/* Timers for fasp(TIMCLK) */
9#define CONFIG_SYS_HZ 1000 /* 1 msec */
10#define CONFIG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */
11
12/*
13 * SDRAM (for initialize)
14 */
15#define CONFIG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */
16#define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */
17
18#define CONFIG_VERY_BIG_RAM /* SynQuacer supports up to 64GB */
19#define CONFIG_MAX_MEM_MAPPED PHYS_SDRAM_SIZE
20
21#define SQ_DRAMINFO_BASE (0x2e00ffc0) /* DRAM info from TF-A */
22
23/*
24 * Boot info
25 */
26#define CONFIG_SYS_INIT_SP_ADDR (0xe0000000) /* stack of init proccess */
27#define CONFIG_SYS_MALLOC_LEN (0x01000000) /* 16Mbyte size of malloc() */
28#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default kernel load address */
29
30/*
31 * Hardware drivers support
32 */
33
34/* RTC */
35#define CONFIG_SYS_I2C_RTC_ADDR 0x51
36
37/* Serial (pl011) */
38#define UART_CLK (62500000)
39#define CONFIG_SERIAL_MULTI
40#define CONFIG_PL011_SERIAL
41#define CONFIG_PL011_CLOCK UART_CLK
42#define CONFIG_PL01x_PORTS {(void *)(0x2a400000)}
43
44#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
45
46/* Support MTD */
47#define CONFIG_SYS_MAX_FLASH_BANKS 1
48#define CONFIG_SYS_FLASH_BASE (0x08000000)
49#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
50
51#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + (512 * 1024))
52#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE)
53
54#define CONFIG_BAUDRATE 115200
55#define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600 }
56
57#define CONFIG_SYS_CBSIZE 1024
58#define CONFIG_SYS_MAXARGS 128
59#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
60
61/* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */
62/* #define CONFIG_SYS_PCI_64BIT 1 */
63
Masami Hiramatsu1d5afdf2021-06-04 18:45:31 +090064#define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \
Masami Hiramatsufe1e5582021-07-12 19:36:12 +090065 "mtd mx66u51235f=u-boot.bin raw 200000 100000;" \
Masami Hiramatsu1d5afdf2021-06-04 18:45:31 +090066 "fip.bin raw 180000 78000;" \
67 "optee.bin raw 500000 100000\0"
68
Masami Hiramatsu7c741272021-06-04 18:45:10 +090069/* Distro boot settings */
70#ifndef CONFIG_SPL_BUILD
71#ifdef CONFIG_CMD_USB
72#define BOOT_TARGET_DEVICE_USB(func) func(USB, usb, 0)
73#else
74#define BOOT_TARGET_DEVICE_USB(func)
75#endif
76
77#ifdef CONFIG_CMD_MMC
78#define BOOT_TARGET_DEVICE_MMC(func) func(MMC, mmc, 0)
79#else
80#define BOOT_TARGET_DEVICE_MMC(func)
81#endif
82
83#ifdef CONFIG_CMD_NVME
84#define BOOT_TARGET_DEVICE_NVME(func) func(NVME, nvme, 0)
85#else
86#define BOOT_TARGET_DEVICE_NVME(func)
87#endif
88
89#ifdef CONFIG_CMD_SCSI
90#define BOOT_TARGET_DEVICE_SCSI(func) func(SCSI, scsi, 0) func(SCSI, scsi, 1)
91#else
92#define BOOT_TARGET_DEVICE_SCSI(func)
93#endif
94
95#define BOOT_TARGET_DEVICES(func) \
96 BOOT_TARGET_DEVICE_USB(func) \
97 BOOT_TARGET_DEVICE_MMC(func) \
98 BOOT_TARGET_DEVICE_SCSI(func) \
99 BOOT_TARGET_DEVICE_NVME(func) \
100
101#include <config_distro_bootcmd.h>
102#else /* CONFIG_SPL_BUILD */
103#define BOOTENV
104#endif
105
106#define CONFIG_EXTRA_ENV_SETTINGS \
107 "fdt_addr_r=0x9fe00000\0" \
108 "kernel_addr_r=0x90000000\0" \
109 "ramdisk_addr_r=0xa0000000\0" \
110 "scriptaddr=0x88000000\0" \
111 "pxefile_addr_r=0x88100000\0" \
Masami Hiramatsu1d5afdf2021-06-04 18:45:31 +0900112 DEFAULT_DFU_ALT_INFO \
Masami Hiramatsu7c741272021-06-04 18:45:10 +0900113 BOOTENV
114
115#endif /* __CONFIG_H */