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git01.mediatek.com / filogic / uboot / bc42971fe14de458c6f039aad390f5d2dd0df2bf / . / board / amcc / redwood / redwood.c
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Feng Kanbc429712008-07-08 22:48:42 -0700[diff] [blame^]1/*
2 * This is the main board level file for the Redwood AMCC board.
3 *
4 * (C) Copyright 2008
5 * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 *
25 */
26
27#include <common.h>
28#include "redwood.h"
29#include <ppc4xx.h>
30#include <asm/processor.h>
31#include <i2c.h>
32#include <asm-ppc/io.h>
33
34int compare_to_true(char *str);
35char *remove_l_w_space(char *in_str);
36char *remove_t_w_space(char *in_str);
37int get_console_port(void);
38
39static void early_init_EBC(void);
40static int bootdevice_selected(void);
41static void early_reinit_EBC(int);
42static void early_init_UIC(void);
43
44/*----------------------------------------------------------------------------+
45| Define Boot devices
46+----------------------------------------------------------------------------*/
47#define BOOT_FROM_8BIT_SRAM 0x00
48#define BOOT_FROM_16BIT_SRAM 0x01
49#define BOOT_FROM_32BIT_SRAM 0x02
50#define BOOT_FROM_8BIT_NAND 0x03
51#define BOOT_FROM_16BIT_NOR 0x04
52#define BOOT_DEVICE_UNKNOWN 0xff
53
54/*----------------------------------------------------------------------------+
55| EBC Devices Characteristics
56| Peripheral Bank Access Parameters - EBC_BxAP
57| Peripheral Bank Configuration Register - EBC_BxCR
58+----------------------------------------------------------------------------*/
59
60/*
61 * 8 bit width SRAM
62 * BU Value
63 * BxAP : 0x03800000 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
64 * B0CR : 0xff098000 - BAS = ff0 - 100 11 00 0000000000000
65 * B2CR : 0xe7098000 - BAS = e70 - 100 11 00 0000000000000
66 */
67#define EBC_BXAP_8BIT_SRAM EBC_BXAP_BME_DISABLED | \
68 EBC_BXAP_TWT_ENCODE(7) | \
69 EBC_BXAP_BCE_DISABLE | \
70 EBC_BXAP_BCT_2TRANS | \
71 EBC_BXAP_CSN_ENCODE(0) | \
72 EBC_BXAP_OEN_ENCODE(0) | \
73 EBC_BXAP_WBN_ENCODE(0) | \
74 EBC_BXAP_WBF_ENCODE(0) | \
75 EBC_BXAP_TH_ENCODE(0) | \
76 EBC_BXAP_RE_DISABLED | \
77 EBC_BXAP_SOR_DELAYED | \
78 EBC_BXAP_BEM_WRITEONLY | \
79 EBC_BXAP_PEN_DISABLED
80
81#define EBC_BXAP_16BIT_SRAM EBC_BXAP_8BIT_SRAM
82#define EBC_BXAP_32BIT_SRAM EBC_BXAP_8BIT_SRAM
83
84/*
85 * NAND flash
86 * BU Value
87 * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
88 * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000
89 * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000
90*/
91#define EBC_BXAP_NAND EBC_BXAP_BME_DISABLED | \
92 EBC_BXAP_TWT_ENCODE(7) | \
93 EBC_BXAP_BCE_DISABLE | \
94 EBC_BXAP_BCT_2TRANS | \
95 EBC_BXAP_CSN_ENCODE(0) | \
96 EBC_BXAP_OEN_ENCODE(0) | \
97 EBC_BXAP_WBN_ENCODE(0) | \
98 EBC_BXAP_WBF_ENCODE(0) | \
99 EBC_BXAP_TH_ENCODE(0) | \
100 EBC_BXAP_RE_DISABLED | \
101 EBC_BXAP_SOR_DELAYED | \
102 EBC_BXAP_BEM_WRITEONLY | \
103 EBC_BXAP_PEN_DISABLED
104
105/*
106 * NOR flash
107 * BU Value
108 * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
109 * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000
110 * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000
111*/
112#define EBC_BXAP_NOR EBC_BXAP_BME_DISABLED | \
113 EBC_BXAP_TWT_ENCODE(7) | \
114 EBC_BXAP_BCE_DISABLE | \
115 EBC_BXAP_BCT_2TRANS | \
116 EBC_BXAP_CSN_ENCODE(0) | \
117 EBC_BXAP_OEN_ENCODE(0) | \
118 EBC_BXAP_WBN_ENCODE(0) | \
119 EBC_BXAP_WBF_ENCODE(0) | \
120 EBC_BXAP_TH_ENCODE(0) | \
121 EBC_BXAP_RE_DISABLED | \
122 EBC_BXAP_SOR_DELAYED | \
123 EBC_BXAP_BEM_WRITEONLY | \
124 EBC_BXAP_PEN_DISABLED
125
126/*
127 * FPGA
128 * BU value :
129 * B1AP = 0x05895240 - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
130 * B1CR = 0xe201a000 - BAS = e20 - 000 11 01 00000000000000
131 */
132#define EBC_BXAP_FPGA EBC_BXAP_BME_DISABLED | \
133 EBC_BXAP_TWT_ENCODE(11) | \
134 EBC_BXAP_BCE_DISABLE | \
135 EBC_BXAP_BCT_2TRANS | \
136 EBC_BXAP_CSN_ENCODE(10) | \
137 EBC_BXAP_OEN_ENCODE(1) | \
138 EBC_BXAP_WBN_ENCODE(1) | \
139 EBC_BXAP_WBF_ENCODE(1) | \
140 EBC_BXAP_TH_ENCODE(1) | \
141 EBC_BXAP_RE_DISABLED | \
142 EBC_BXAP_SOR_DELAYED | \
143 EBC_BXAP_BEM_RW | \
144 EBC_BXAP_PEN_DISABLED
145
146#define EBC_BXCR_8BIT_SRAM_CS0 EBC_BXCR_BAS_ENCODE(0xFFE00000) | \
147 EBC_BXCR_BS_1MB | \
148 EBC_BXCR_BU_RW | \
149 EBC_BXCR_BW_8BIT
150
151#define EBC_BXCR_32BIT_SRAM_CS0 EBC_BXCR_BAS_ENCODE(0xFFC00000) | \
152 EBC_BXCR_BS_1MB | \
153 EBC_BXCR_BU_RW | \
154 EBC_BXCR_BW_32BIT
155
156#define EBC_BXCR_NAND_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \
157 EBC_BXCR_BS_16MB | \
158 EBC_BXCR_BU_RW | \
159 EBC_BXCR_BW_8BIT
160
161#define EBC_BXCR_16BIT_SRAM_CS0 EBC_BXCR_BAS_ENCODE(0xFFE00000) | \
162 EBC_BXCR_BS_2MB | \
163 EBC_BXCR_BU_RW | \
164 EBC_BXCR_BW_16BIT
165
166#define EBC_BXCR_NOR_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \
167 EBC_BXCR_BS_16MB | \
168 EBC_BXCR_BU_RW | \
169 EBC_BXCR_BW_16BIT
170
171#define EBC_BXCR_NOR_CS1 EBC_BXCR_BAS_ENCODE(0xE0000000) | \
172 EBC_BXCR_BS_128MB | \
173 EBC_BXCR_BU_RW | \
174 EBC_BXCR_BW_16BIT
175
176#define EBC_BXCR_NAND_CS1 EBC_BXCR_BAS_ENCODE(0xE0000000) | \
177 EBC_BXCR_BS_128MB | \
178 EBC_BXCR_BU_RW | \
179 EBC_BXCR_BW_8BIT
180
181#define EBC_BXCR_NAND_CS2 EBC_BXCR_BAS_ENCODE(0xC0000000) | \
182 EBC_BXCR_BS_128MB | \
183 EBC_BXCR_BU_RW | \
184 EBC_BXCR_BW_8BIT
185
186#define EBC_BXCR_SRAM_CS2 EBC_BXCR_BAS_ENCODE(0xC0000000) | \
187 EBC_BXCR_BS_4MB | \
188 EBC_BXCR_BU_RW | \
189 EBC_BXCR_BW_32BIT
190
191#define EBC_BXCR_LARGE_FLASH_CS2 EBC_BXCR_BAS_ENCODE(0xE7000000) | \
192 EBC_BXCR_BS_16MB | \
193 EBC_BXCR_BU_RW | \
194 EBC_BXCR_BW_16BIT
195
196#define EBC_BXCR_FPGA_CS3 EBC_BXCR_BAS_ENCODE(0xe2000000) | \
197 EBC_BXCR_BS_1MB | \
198 EBC_BXCR_BU_RW | \
199 EBC_BXCR_BW_16BIT
200
201/*****************************************************************************
202 * UBOOT initiated board specific function calls
203 ****************************************************************************/
204
205int board_early_init_f(void)
206{
207 int computed_boot_device = BOOT_DEVICE_UNKNOWN;
208
209 /*
210 * Initialise EBC
211 */
212 early_init_EBC();
213
214 /*
215 * Determine which boot device was selected
216 */
217 computed_boot_device = bootdevice_selected();
218
219 /*
220 * Reinit EBC based on selected boot device
221 */
222 early_reinit_EBC(computed_boot_device);
223
224 /*
225 * Setup for UIC on 460SX redwood board
226 */
227 early_init_UIC();
228
229 return 0;
230}
231
232int checkboard(void)
233{
234 char *s = getenv("serial#");
235
236 printf("Board: Redwood - AMCC 460SX Reference Board");
237 if (s != NULL) {
238 puts(", serial# ");
239 puts(s);
240 }
241 putc('\n');
242
243 return 0;
244}
245
246static void early_init_EBC(void)
247{
248 /*-------------------------------------------------------------------+
249 | Initialize EBC CONFIG -
250 | Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
251 | default value :
252 | 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
253 |
254 +-------------------------------------------------------------------*/
255 mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
256 EBC_CFG_PTD_ENABLE |
257 EBC_CFG_RTC_16PERCLK |
258 EBC_CFG_ATC_PREVIOUS |
259 EBC_CFG_DTC_PREVIOUS |
260 EBC_CFG_CTC_PREVIOUS |
261 EBC_CFG_OEO_PREVIOUS |
262 EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | EBC_CFG_PR_16);
263
264 /*-------------------------------------------------------------------+
265 |
266 | PART 1 : Initialize EBC Bank 3
267 | ==============================
268 | Bank1 is always associated to the EPLD.
269 | It has to be initialized prior to other banks settings computation
270 | since some board registers values may be needed to determine the
271 | boot type
272 |
273 +-------------------------------------------------------------------*/
274 mtebc(pb1ap, EBC_BXAP_FPGA);
275 mtebc(pb1cr, EBC_BXCR_FPGA_CS3);
276
277}
278
279static int bootdevice_selected(void)
280{
281 unsigned long sdr0_pinstp;
282 unsigned long bootstrap_settings;
283 int computed_boot_device = BOOT_DEVICE_UNKNOWN;
284
285 /*-------------------------------------------------------------------+
286 |
287 | Determine which boot device was selected
288 | =================================================
289 |
290 | Read Pin Strap Register in PPC460SX
291 | Result can either be :
292 | - Boot strap = boot from EBC 8bits => Small Flash
293 | - Boot strap = boot from PCI
294 | - Boot strap = IIC
295 | In case of boot from IIC, read Serial Device Strap Register1
296 |
297 | Result can either be :
298 | - Boot from EBC - EBC Bus Width = 8bits => Small Flash
299 | - Boot from EBC - EBC Bus Width = 16bits => Large Flash or SRAM
300 | - Boot from PCI
301 |
302 +-------------------------------------------------------------------*/
303 /* Read Pin Strap Register in PPC460SX */
304 mfsdr(SDR0_PINSTP, sdr0_pinstp);
305 bootstrap_settings = sdr0_pinstp & SDR0_PSTRP0_BOOTSTRAP_MASK;
306
307 switch (bootstrap_settings) {
308 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
309 /*
310 * Boot from SRAM, 8bit width
311 */
312 computed_boot_device = BOOT_FROM_8BIT_SRAM;
313 break;
314 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
315 /*
316 * Boot from SRAM, 32bit width
317 */
318 computed_boot_device = BOOT_FROM_32BIT_SRAM;
319 break;
320 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
321 /*
322 * Boot from NAND, 8bit width
323 */
324 computed_boot_device = BOOT_FROM_8BIT_NAND;
325 break;
326 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
327 /*
328 * Boot from SRAM, 16bit width
329 * Boot setting in IIC EEPROM 0x50
330 */
331 computed_boot_device = BOOT_FROM_16BIT_SRAM;
332 break;
333 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS5:
334 /*
335 * Boot from NOR, 16bit width
336 * Boot setting in IIC EEPROM 0x54
337 */
338 computed_boot_device = BOOT_FROM_16BIT_NOR;
339 break;
340 default:
341 /* should not be */
342 computed_boot_device = BOOT_DEVICE_UNKNOWN;
343 break;
344 }
345
346 return computed_boot_device;
347}
348
349static void early_reinit_EBC(int computed_boot_device)
350{
351 /*-------------------------------------------------------------------+
352 |
353 | Compute EBC settings depending on selected boot device
354 | ====== ======================================================
355 |
356 | Resulting EBC init will be among following configurations :
357 |
358 | - Boot from EBC 8bits => boot from Small Flash selected
359 | EBC-CS0 = Small Flash
360 | EBC-CS2 = Large Flash and SRAM
361 |
362 | - Boot from EBC 16bits => boot from Large Flash or SRAM
363 | EBC-CS0 = Large Flash or SRAM
364 | EBC-CS2 = Small Flash
365 |
366 | - Boot from PCI
367 | EBC-CS0 = not initialized to avoid address contention
368 | EBC-CS2 = same as boot from Small Flash selected
369 |
370 +-------------------------------------------------------------------*/
371 unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
372 unsigned long ebc0_cs1_bxap_value = 0, ebc0_cs1_bxcr_value = 0;
373 unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;
374
375 switch (computed_boot_device) {
376 /*-------------------------------------------------------------------*/
377 case BOOT_FROM_8BIT_SRAM:
378 /*-------------------------------------------------------------------*/
379 ebc0_cs0_bxap_value = EBC_BXAP_8BIT_SRAM;
380 ebc0_cs0_bxcr_value = EBC_BXCR_8BIT_SRAM_CS0;
381 ebc0_cs1_bxap_value = EBC_BXAP_NOR;
382 ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
383 ebc0_cs2_bxap_value = EBC_BXAP_NAND;
384 ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
385 break;
386
387 /*-------------------------------------------------------------------*/
388 case BOOT_FROM_16BIT_SRAM:
389 /*-------------------------------------------------------------------*/
390 ebc0_cs0_bxap_value = EBC_BXAP_16BIT_SRAM;
391 ebc0_cs0_bxcr_value = EBC_BXCR_16BIT_SRAM_CS0;
392 ebc0_cs1_bxap_value = EBC_BXAP_NOR;
393 ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
394 ebc0_cs2_bxap_value = EBC_BXAP_NAND;
395 ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
396 break;
397
398 /*-------------------------------------------------------------------*/
399 case BOOT_FROM_32BIT_SRAM:
400 /*-------------------------------------------------------------------*/
401 ebc0_cs0_bxap_value = EBC_BXAP_32BIT_SRAM;
402 ebc0_cs0_bxcr_value = EBC_BXCR_32BIT_SRAM_CS0;
403 ebc0_cs1_bxap_value = EBC_BXAP_NOR;
404 ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
405 ebc0_cs2_bxap_value = EBC_BXAP_NAND;
406 ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
407 break;
408
409 /*-------------------------------------------------------------------*/
410 case BOOT_FROM_16BIT_NOR:
411 /*-------------------------------------------------------------------*/
412 ebc0_cs0_bxap_value = EBC_BXAP_NOR;
413 ebc0_cs0_bxcr_value = EBC_BXCR_NOR_CS0;
414 ebc0_cs1_bxap_value = EBC_BXAP_NAND;
415 ebc0_cs1_bxcr_value = EBC_BXCR_NAND_CS1;
416 ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM;
417 ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2;
418 break;
419
420 /*-------------------------------------------------------------------*/
421 case BOOT_FROM_8BIT_NAND:
422 /*-------------------------------------------------------------------*/
423 ebc0_cs0_bxap_value = EBC_BXAP_NAND;
424 ebc0_cs0_bxcr_value = EBC_BXCR_NAND_CS0;
425 ebc0_cs1_bxap_value = EBC_BXAP_NOR;
426 ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
427 ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM;
428 ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2;
429 break;
430
431 /*-------------------------------------------------------------------*/
432 default:
433 /*-------------------------------------------------------------------*/
434 /* BOOT_DEVICE_UNKNOWN */
435 break;
436 }
437
438 mtebc(pb0ap, ebc0_cs0_bxap_value);
439 mtebc(pb0cr, ebc0_cs0_bxcr_value);
440 mtebc(pb1ap, ebc0_cs1_bxap_value);
441 mtebc(pb1cr, ebc0_cs1_bxcr_value);
442 mtebc(pb2ap, ebc0_cs2_bxap_value);
443 mtebc(pb2cr, ebc0_cs2_bxcr_value);
444}
445
446static void early_init_UIC(void)
447{
448 /*--------------------------------------------------------------------+
449 | Initialise UIC registers. Clear all interrupts. Disable all
450 | interrupts.
451 | Set critical interrupt values. Set interrupt polarities. Set
452 | interrupt trigger levels. Make bit 0 High priority. Clear all
453 | interrupts again.
454 +-------------------------------------------------------------------*/
455 mtdcr(uic3sr, 0xffffffff); /* Clear all interrupts */
456 mtdcr(uic3er, 0x00000000); /* disable all interrupts */
457 mtdcr(uic3cr, 0x00000000); /* Set Critical / Non Critical
458 * interrupts */
459 mtdcr(uic3pr, 0xffffffff); /* Set Interrupt Polarities */
460 mtdcr(uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */
461 mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */
462 mtdcr(uic3sr, 0xffffffff); /* clear all interrupts */
463
464 mtdcr(uic2sr, 0xffffffff); /* Clear all interrupts */
465 mtdcr(uic2er, 0x00000000); /* disable all interrupts */
466 mtdcr(uic2cr, 0x00000000); /* Set Critical / Non Critical
467 * interrupts */
468 mtdcr(uic2pr, 0xebebebff); /* Set Interrupt Polarities */
469 mtdcr(uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */
470 mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
471 mtdcr(uic2sr, 0xffffffff); /* clear all interrupts */
472
473 mtdcr(uic1sr, 0xffffffff); /* Clear all interrupts */
474 mtdcr(uic1er, 0x00000000); /* disable all interrupts */
475 mtdcr(uic1cr, 0x00000000); /* Set Critical / Non Critical
476 * interrupts */
477 mtdcr(uic1pr, 0xffffffff); /* Set Interrupt Polarities */
478 mtdcr(uic1tr, 0x001fc0ff); /* Set Interrupt Trigger Levels */
479 mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
480 mtdcr(uic1sr, 0xffffffff); /* clear all interrupts */
481
482 mtdcr(uic0sr, 0xffffffff); /* Clear all interrupts */
483 mtdcr(uic0er, 0x00000000); /* disable all interrupts excepted
484 * cascade to be checked */
485 mtdcr(uic0cr, 0x00104001); /* Set Critical / Non Critical
486 * interrupts */
487 mtdcr(uic0pr, 0xffffffff); /* Set Interrupt Polarities */
488 mtdcr(uic0tr, 0x000f003c); /* Set Interrupt Trigger Levels */
489 mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
490 mtdcr(uic0sr, 0xffffffff); /* clear all interrupts */
491
492}