blob: a40b377bcaac14947a7a04748c305551bd4a73b2 [file] [log] [blame]
wdenkaffae2b2002-08-17 09:36:01 +00001/*
2 * (C) Copyright 2002
3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 */
24
25#include <common.h>
26#include <asm/processor.h>
27#include <asm/mmu.h>
Becky Bruce42b400e2008-08-04 14:01:53 -050028#include <asm/io.h>
wdenkaffae2b2002-08-17 09:36:01 +000029
30int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower)
31{
Becky Bruce42b400e2008-08-04 14:01:53 -050032 sync();
33
wdenkaffae2b2002-08-17 09:36:01 +000034 switch (bat) {
Becky Bruce065b5772008-05-15 21:29:04 -050035 case DBAT0:
36 mtspr (DBAT0L, lower);
37 mtspr (DBAT0U, upper);
38 break;
wdenkaffae2b2002-08-17 09:36:01 +000039 case IBAT0:
40 mtspr (IBAT0L, lower);
41 mtspr (IBAT0U, upper);
42 break;
Becky Bruce065b5772008-05-15 21:29:04 -050043 case DBAT1:
44 mtspr (DBAT1L, lower);
45 mtspr (DBAT1U, upper);
46 break;
wdenkaffae2b2002-08-17 09:36:01 +000047 case IBAT1:
48 mtspr (IBAT1L, lower);
49 mtspr (IBAT1U, upper);
50 break;
Becky Bruce065b5772008-05-15 21:29:04 -050051 case DBAT2:
52 mtspr (DBAT2L, lower);
53 mtspr (DBAT2U, upper);
54 break;
wdenkaffae2b2002-08-17 09:36:01 +000055 case IBAT2:
56 mtspr (IBAT2L, lower);
57 mtspr (IBAT2U, upper);
58 break;
Becky Bruce065b5772008-05-15 21:29:04 -050059 case DBAT3:
60 mtspr (DBAT3L, lower);
61 mtspr (DBAT3U, upper);
62 break;
wdenkaffae2b2002-08-17 09:36:01 +000063 case IBAT3:
64 mtspr (IBAT3L, lower);
65 mtspr (IBAT3U, upper);
66 break;
Becky Bruce065b5772008-05-15 21:29:04 -050067#ifdef CONFIG_HIGH_BATS
68 case DBAT4:
69 mtspr (DBAT4L, lower);
70 mtspr (DBAT4U, upper);
wdenkaffae2b2002-08-17 09:36:01 +000071 break;
Becky Bruce065b5772008-05-15 21:29:04 -050072 case IBAT4:
73 mtspr (IBAT4L, lower);
74 mtspr (IBAT4U, upper);
wdenkaffae2b2002-08-17 09:36:01 +000075 break;
Becky Bruce065b5772008-05-15 21:29:04 -050076 case DBAT5:
77 mtspr (DBAT5L, lower);
78 mtspr (DBAT5U, upper);
wdenkaffae2b2002-08-17 09:36:01 +000079 break;
Becky Bruce065b5772008-05-15 21:29:04 -050080 case IBAT5:
81 mtspr (IBAT5L, lower);
82 mtspr (IBAT5U, upper);
wdenkaffae2b2002-08-17 09:36:01 +000083 break;
Becky Bruce065b5772008-05-15 21:29:04 -050084 case DBAT6:
85 mtspr (DBAT6L, lower);
86 mtspr (DBAT6U, upper);
87 break;
88 case IBAT6:
89 mtspr (IBAT6L, lower);
90 mtspr (IBAT6U, upper);
91 break;
92 case DBAT7:
93 mtspr (DBAT7L, lower);
94 mtspr (DBAT7U, upper);
95 break;
96 case IBAT7:
97 mtspr (IBAT7L, lower);
98 mtspr (IBAT7U, upper);
99 break;
100#endif
wdenkaffae2b2002-08-17 09:36:01 +0000101 default:
102 return (-1);
103 }
104
Becky Bruce42b400e2008-08-04 14:01:53 -0500105 sync();
106 isync();
107
wdenkaffae2b2002-08-17 09:36:01 +0000108 return (0);
109}
110
111int read_bat (ppc_bat_t bat, unsigned long *upper, unsigned long *lower)
112{
113 unsigned long register u;
114 unsigned long register l;
115
116 switch (bat) {
Becky Bruce065b5772008-05-15 21:29:04 -0500117 case DBAT0:
118 l = mfspr (DBAT0L);
119 u = mfspr (DBAT0U);
120 break;
wdenkaffae2b2002-08-17 09:36:01 +0000121 case IBAT0:
122 l = mfspr (IBAT0L);
123 u = mfspr (IBAT0U);
124 break;
Becky Bruce065b5772008-05-15 21:29:04 -0500125 case DBAT1:
126 l = mfspr (DBAT1L);
127 u = mfspr (DBAT1U);
128 break;
wdenkaffae2b2002-08-17 09:36:01 +0000129 case IBAT1:
130 l = mfspr (IBAT1L);
131 u = mfspr (IBAT1U);
132 break;
Becky Bruce065b5772008-05-15 21:29:04 -0500133 case DBAT2:
134 l = mfspr (DBAT2L);
135 u = mfspr (DBAT2U);
136 break;
wdenkaffae2b2002-08-17 09:36:01 +0000137 case IBAT2:
138 l = mfspr (IBAT2L);
139 u = mfspr (IBAT2U);
140 break;
Becky Bruce065b5772008-05-15 21:29:04 -0500141 case DBAT3:
142 l = mfspr (DBAT3L);
143 u = mfspr (DBAT3U);
144 break;
wdenkaffae2b2002-08-17 09:36:01 +0000145 case IBAT3:
146 l = mfspr (IBAT3L);
147 u = mfspr (IBAT3U);
148 break;
Becky Bruce065b5772008-05-15 21:29:04 -0500149#ifdef CONFIG_HIGH_BATS
150 case DBAT4:
151 l = mfspr (DBAT4L);
152 u = mfspr (DBAT4U);
wdenkaffae2b2002-08-17 09:36:01 +0000153 break;
Becky Bruce065b5772008-05-15 21:29:04 -0500154 case IBAT4:
155 l = mfspr (IBAT4L);
156 u = mfspr (IBAT4U);
wdenkaffae2b2002-08-17 09:36:01 +0000157 break;
Becky Bruce065b5772008-05-15 21:29:04 -0500158 case DBAT5:
159 l = mfspr (DBAT5L);
160 u = mfspr (DBAT5U);
wdenkaffae2b2002-08-17 09:36:01 +0000161 break;
Becky Bruce065b5772008-05-15 21:29:04 -0500162 case IBAT5:
163 l = mfspr (IBAT5L);
164 u = mfspr (IBAT5U);
wdenkaffae2b2002-08-17 09:36:01 +0000165 break;
Becky Bruce065b5772008-05-15 21:29:04 -0500166 case DBAT6:
167 l = mfspr (DBAT6L);
168 u = mfspr (DBAT6U);
169 break;
170 case IBAT6:
171 l = mfspr (IBAT6L);
172 u = mfspr (IBAT6U);
173 break;
174 case DBAT7:
175 l = mfspr (DBAT7L);
176 u = mfspr (DBAT7U);
177 break;
178 case IBAT7:
179 l = mfspr (IBAT7L);
180 u = mfspr (IBAT7U);
181 break;
182#endif
wdenkaffae2b2002-08-17 09:36:01 +0000183 default:
184 return (-1);
185 }
186
187 *upper = u;
188 *lower = l;
189
190 return (0);
191}
Becky Brucee7efd5b2008-05-09 15:41:35 -0500192
193void print_bats(void)
194{
195 printf("BAT registers:\n");
196
197 printf ("\tIBAT0L = 0x%08X ", mfspr (IBAT0L));
198 printf ("\tIBAT0U = 0x%08X\n", mfspr (IBAT0U));
199 printf ("\tDBAT0L = 0x%08X ", mfspr (DBAT0L));
200 printf ("\tDBAT0U = 0x%08X\n", mfspr (DBAT0U));
201 printf ("\tIBAT1L = 0x%08X ", mfspr (IBAT1L));
202 printf ("\tIBAT1U = 0x%08X\n", mfspr (IBAT1U));
203 printf ("\tDBAT1L = 0x%08X ", mfspr (DBAT1L));
204 printf ("\tDBAT1U = 0x%08X\n", mfspr (DBAT1U));
205 printf ("\tIBAT2L = 0x%08X ", mfspr (IBAT2L));
206 printf ("\tIBAT2U = 0x%08X\n", mfspr (IBAT2U));
207 printf ("\tDBAT2L = 0x%08X ", mfspr (DBAT2L));
208 printf ("\tDBAT2U = 0x%08X\n", mfspr (DBAT2U));
209 printf ("\tIBAT3L = 0x%08X ", mfspr (IBAT3L));
210 printf ("\tIBAT3U = 0x%08X\n", mfspr (IBAT3U));
211 printf ("\tDBAT3L = 0x%08X ", mfspr (DBAT3L));
212 printf ("\tDBAT3U = 0x%08X\n", mfspr (DBAT3U));
213
214#ifdef CONFIG_HIGH_BATS
215 printf ("\tIBAT4L = 0x%08X ", mfspr (IBAT4L));
216 printf ("\tIBAT4U = 0x%08X\n", mfspr (IBAT4U));
217 printf ("\tDBAT4L = 0x%08X ", mfspr (DBAT4L));
218 printf ("\tDBAT4U = 0x%08X\n", mfspr (DBAT4U));
219 printf ("\tIBAT5L = 0x%08X ", mfspr (IBAT5L));
220 printf ("\tIBAT5U = 0x%08X\n", mfspr (IBAT5U));
221 printf ("\tDBAT5L = 0x%08X ", mfspr (DBAT5L));
222 printf ("\tDBAT5U = 0x%08X\n", mfspr (DBAT5U));
223 printf ("\tIBAT6L = 0x%08X ", mfspr (IBAT6L));
224 printf ("\tIBAT6U = 0x%08X\n", mfspr (IBAT6U));
225 printf ("\tDBAT6L = 0x%08X ", mfspr (DBAT6L));
226 printf ("\tDBAT6U = 0x%08X\n", mfspr (DBAT6U));
227 printf ("\tIBAT7L = 0x%08X ", mfspr (IBAT7L));
228 printf ("\tIBAT7U = 0x%08X\n", mfspr (IBAT7U));
229 printf ("\tDBAT7L = 0x%08X ", mfspr (DBAT7L));
230 printf ("\tDBAT7U = 0x%08X\n", mfspr (DBAT7U));
231#endif
232}