Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 1 | /* Configuration header file for Gaisler Research AB's Template |
| 2 | * design (GPL Open Source SPARC/LEON3 96MHz) for Altera NIOS |
| 3 | * Development board Stratix II edition, with the FPGA device |
| 4 | * EP2S60. |
| 5 | * |
| 6 | * (C) Copyright 2003-2005 |
| 7 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 8 | * |
| 9 | * (C) Copyright 2008 |
| 10 | * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. |
| 11 | * |
Wolfgang Denk | bd8ec7e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 12 | * SPDX-License-Identifier: GPL-2.0+ |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | #ifndef __CONFIG_H__ |
| 16 | #define __CONFIG_H__ |
| 17 | |
| 18 | /* |
| 19 | * High Level Configuration Options |
| 20 | * (easy to change) |
| 21 | */ |
| 22 | |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 23 | /* Altera NIOS Development board, Stratix II board */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 24 | #define CONFIG_GR_EP2S60 1 |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 25 | |
| 26 | /* CPU / AMBA BUS configuration */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 27 | #define CONFIG_SYS_CLK_FREQ 96000000 /* 96MHz */ |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 28 | |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 29 | /* Define this is the GR-2S60-MEZZ mezzanine is available and you |
| 30 | * want to use the USB and GRETH functionality of the board |
| 31 | */ |
| 32 | #undef GR_2S60_MEZZ |
| 33 | |
| 34 | #ifdef GR_2S60_MEZZ |
| 35 | #define USE_GRETH 1 |
| 36 | #define USE_GRUSB 1 |
| 37 | #endif |
| 38 | |
| 39 | /* |
| 40 | * Serial console configuration |
| 41 | */ |
| 42 | #define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 43 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 44 | |
| 45 | /* Partitions */ |
| 46 | #define CONFIG_DOS_PARTITION |
| 47 | #define CONFIG_MAC_PARTITION |
| 48 | #define CONFIG_ISO_PARTITION |
| 49 | |
| 50 | /* |
| 51 | * Supported commands |
| 52 | */ |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 53 | #define CONFIG_CMD_REGINFO |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 54 | #define CONFIG_CMD_DIAG |
| 55 | #define CONFIG_CMD_IRQ |
| 56 | |
| 57 | /* USB support */ |
| 58 | #if USE_GRUSB |
| 59 | #define CONFIG_USB_UHCI |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 60 | /* Enable needed helper functions */ |
Jean-Christophe PLAGNIOL-VILLARD | 2a7a031 | 2009-05-16 12:14:54 +0200 | [diff] [blame] | 61 | #define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */ |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 62 | #endif |
| 63 | |
| 64 | /* |
| 65 | * Autobooting |
| 66 | */ |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 67 | |
| 68 | #define CONFIG_PREBOOT "echo;" \ |
| 69 | "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ |
| 70 | "echo" |
| 71 | |
| 72 | #undef CONFIG_BOOTARGS |
| 73 | |
| 74 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 75 | "netdev=eth0\0" \ |
| 76 | "nfsargs=setenv bootargs console=ttyS0,38400 root=/dev/nfs rw " \ |
| 77 | "nfsroot=${serverip}:${rootpath}\0" \ |
| 78 | "ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram rw\0" \ |
| 79 | "addip=setenv bootargs ${bootargs} " \ |
| 80 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ |
| 81 | ":${hostname}:${netdev}:off panic=1\0" \ |
| 82 | "flash_nfs=run nfsargs addip;" \ |
| 83 | "bootm ${kernel_addr}\0" \ |
| 84 | "flash_self=run ramargs addip;" \ |
| 85 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
| 86 | "net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0" \ |
| 87 | "scratch=40800000\0" \ |
Mike Frysinger | c3c6bf1 | 2011-10-12 19:47:51 +0000 | [diff] [blame] | 88 | "getkernel=tftpboot $(scratch) $(bootfile)\0" \ |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 89 | "bootargs=console=ttyS0,38400 root=/dev/nfs rw nfsroot=192.168.0.20:/export/rootfs ip=192.168.0.207:192.168.0.20:192.168.0.1:255.255.255.0:ml401:eth0\0" \ |
| 90 | "" |
| 91 | |
| 92 | #define CONFIG_NETMASK 255.255.255.0 |
| 93 | #define CONFIG_GATEWAYIP 192.168.0.1 |
| 94 | #define CONFIG_SERVERIP 192.168.0.20 |
| 95 | #define CONFIG_IPADDR 192.168.0.207 |
Joe Hershberger | 257ff78 | 2011-10-13 13:03:47 +0000 | [diff] [blame] | 96 | #define CONFIG_ROOTPATH "/export/rootfs" |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 97 | #define CONFIG_HOSTNAME ml401 |
Joe Hershberger | e4da248 | 2011-10-13 13:03:48 +0000 | [diff] [blame] | 98 | #define CONFIG_BOOTFILE "/uImage" |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 99 | |
| 100 | #define CONFIG_BOOTCOMMAND "run flash_self" |
| 101 | |
| 102 | /* Memory MAP |
| 103 | * |
| 104 | * Flash: |
| 105 | * |--------------------------------| |
| 106 | * | 0x00000000 Text & Data & BSS | * |
| 107 | * | for Monitor | * |
| 108 | * | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| * |
| 109 | * | UNUSED / Growth | * 256kb |
| 110 | * |--------------------------------| |
| 111 | * | 0x00050000 Base custom area | * |
| 112 | * | kernel / FS | * |
| 113 | * | | * Rest of Flash |
| 114 | * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| |
| 115 | * | END-0x00008000 Environment | * 32kb |
| 116 | * |--------------------------------| |
| 117 | * |
| 118 | * |
| 119 | * |
| 120 | * Main Memory: |
| 121 | * |--------------------------------| |
| 122 | * | UNUSED / scratch area | |
| 123 | * | | |
| 124 | * | | |
| 125 | * | | |
| 126 | * | | |
| 127 | * |--------------------------------| |
| 128 | * | Monitor .Text / .DATA / .BSS | * 512kb |
| 129 | * | Relocated! | * |
| 130 | * |--------------------------------| |
| 131 | * | Monitor Malloc | * 128kb (contains relocated environment) |
| 132 | * |--------------------------------| |
| 133 | * | Monitor/kernel STACK | * 64kb |
| 134 | * |--------------------------------| |
| 135 | * | Page Table for MMU systems | * 2k |
| 136 | * |--------------------------------| |
| 137 | * | PROM Code accessed from Linux | * 6kb-128b |
| 138 | * |--------------------------------| |
| 139 | * | Global data (avail from kernel)| * 128b |
| 140 | * |--------------------------------| |
| 141 | * |
| 142 | */ |
| 143 | |
| 144 | /* |
| 145 | * Flash configuration (8,16 or 32 MB) |
| 146 | * TEXT base always at 0xFFF00000 |
| 147 | * ENV_ADDR always at 0xFFF40000 |
| 148 | * FLASH_BASE at 0xFC000000 for 64 MB |
| 149 | * 0xFE000000 for 32 MB |
| 150 | * 0xFF000000 for 16 MB |
| 151 | * 0xFF800000 for 8 MB |
| 152 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 153 | /*#define CONFIG_SYS_NO_FLASH 1*/ |
| 154 | #define CONFIG_SYS_FLASH_BASE 0x00000000 |
| 155 | #define CONFIG_SYS_FLASH_SIZE 0x00400000 /* FPGA Bit file is in top of FLASH, we only ues the bottom 4Mb */ |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 156 | |
| 157 | #define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 158 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ |
| 159 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 160 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 161 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
| 162 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ |
| 163 | #define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ |
| 164 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ |
| 165 | #define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 166 | |
| 167 | /*** CFI CONFIG ***/ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 168 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT |
Jean-Christophe PLAGNIOL-VILLARD | 8d94c23 | 2008-08-13 01:40:42 +0200 | [diff] [blame] | 169 | #define CONFIG_FLASH_CFI_DRIVER |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 170 | #define CONFIG_SYS_FLASH_CFI |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 171 | /* Bypass cache when reading regs from flash memory */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 172 | #define CONFIG_SYS_FLASH_CFI_BYPASS_READ |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 173 | /* Buffered writes (32byte/go) instead of single accesses */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 174 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 175 | |
| 176 | /* |
| 177 | * Environment settings |
| 178 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 68a8756 | 2008-09-10 22:48:00 +0200 | [diff] [blame] | 179 | /*#define CONFIG_ENV_IS_NOWHERE 1*/ |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 180 | #define CONFIG_ENV_IS_IN_FLASH 1 |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 181 | /* CONFIG_ENV_ADDR need to be at sector boundary */ |
| 182 | #define CONFIG_ENV_SIZE 0x8000 |
| 183 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 184 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE) |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 185 | #define CONFIG_ENV_OVERWRITE 1 |
| 186 | |
| 187 | /* |
| 188 | * Memory map |
| 189 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 190 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
| 191 | #define CONFIG_SYS_SDRAM_SIZE 0x02000000 |
| 192 | #define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE) |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 193 | |
| 194 | /* no SRAM available */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 195 | #undef CONFIG_SYS_SRAM_BASE |
| 196 | #undef CONFIG_SYS_SRAM_SIZE |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 197 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 198 | #define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE |
| 199 | #define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE |
| 200 | #define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 201 | |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 202 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_END - GENERATED_GBL_DATA_SIZE) |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 203 | |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 204 | #define CONFIG_SYS_PROM_SIZE (8192-GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 205 | #define CONFIG_SYS_PROM_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE) |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 206 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 207 | #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_PROM_OFFSET-32) |
| 208 | #define CONFIG_SYS_STACK_SIZE (0x10000-32) |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 209 | |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 210 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 211 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
| 212 | # define CONFIG_SYS_RAMBOOT 1 |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 213 | #endif |
| 214 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 215 | #define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ |
| 216 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
| 217 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 218 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 219 | #define CONFIG_SYS_MALLOC_END (CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE) |
| 220 | #define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN) |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 221 | |
| 222 | /* relocated monitor area */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 223 | #define CONFIG_SYS_RELOC_MONITOR_MAX_END CONFIG_SYS_MALLOC_BASE |
| 224 | #define CONFIG_SYS_RELOC_MONITOR_BASE (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN) |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 225 | |
| 226 | /* make un relocated address from relocated address */ |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 227 | #define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE)) |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 228 | |
| 229 | /* |
| 230 | * Ethernet configuration uses on board SMC91C111, however if a mezzanine |
| 231 | * with a PHY is attached the GRETH can be used on this board. |
| 232 | * Define USE_GRETH in order to use the mezzanine provided PHY with the |
| 233 | * onchip GRETH network MAC, note that this is not supported by the |
| 234 | * template design. |
| 235 | */ |
| 236 | #ifndef USE_GRETH |
| 237 | |
| 238 | /* USE SMC91C111 MAC */ |
Ben Warren | 0fd6aae | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 239 | #define CONFIG_SMC91111 1 |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 240 | #define CONFIG_SMC91111_BASE 0x20000300 /* chip select 3 */ |
| 241 | #define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */ |
| 242 | #undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */ |
| 243 | /*#define CONFIG_SHOW_ACTIVITY*/ |
| 244 | #define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ |
| 245 | |
| 246 | #else |
| 247 | |
| 248 | /* USE GRETH Ethernet Driver */ |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 249 | #define CONFIG_GRETH 1 |
Masahiro Yamada | cbafcdf | 2015-05-26 10:58:31 +0900 | [diff] [blame] | 250 | #endif |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 251 | |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 252 | #define CONFIG_PHY_ADDR 0x00 |
| 253 | |
| 254 | /* |
| 255 | * Miscellaneous configurable options |
| 256 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 257 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 258 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 259 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 260 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 261 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 262 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 263 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 264 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 265 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 266 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 267 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
| 268 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 269 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 270 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 271 | |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 272 | /*----------------------------------------------------------------------- |
| 273 | * USB stuff |
| 274 | *----------------------------------------------------------------------- |
| 275 | */ |
| 276 | #define CONFIG_USB_CLOCK 0x0001BBBB |
| 277 | #define CONFIG_USB_CONFIG 0x00005000 |
| 278 | |
| 279 | /***** Gaisler GRLIB IP-Cores Config ********/ |
| 280 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 281 | #define CONFIG_SYS_GRLIB_SDRAM 0 |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 282 | |
Daniel Hellstrom | a7da6a0 | 2010-01-25 09:56:08 +0100 | [diff] [blame] | 283 | /* No SDRAM Configuration */ |
| 284 | #undef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1 |
| 285 | |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 286 | /* See, GRLIB Docs (grip.pdf) on how to set up |
| 287 | * These the memory controller registers. |
| 288 | */ |
Daniel Hellstrom | a7da6a0 | 2010-01-25 09:56:08 +0100 | [diff] [blame] | 289 | #define CONFIG_SYS_GRLIB_ESA_MCTRL1 |
| 290 | #define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1 (0x10f800ff | (1<<11)) |
| 291 | #define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2 0x00000000 |
| 292 | #define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3 0x00000000 |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 293 | |
Daniel Hellstrom | a7da6a0 | 2010-01-25 09:56:08 +0100 | [diff] [blame] | 294 | /* GRLIB FT-MCTRL configuration */ |
| 295 | #define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1 |
| 296 | #define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1 (0x10f800ff | (1<<11)) |
| 297 | #define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2 0x00000000 |
| 298 | #define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3 0x00000000 |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 299 | |
Daniel Hellstrom | a7da6a0 | 2010-01-25 09:56:08 +0100 | [diff] [blame] | 300 | /* DDR controller */ |
| 301 | #define CONFIG_SYS_GRLIB_GAISLER_DDRSPA1 |
| 302 | #define CONFIG_SYS_GRLIB_GAISLER_DDRSPA1_CTRL 0xa900830a |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 303 | |
Daniel Hellstrom | a7da6a0 | 2010-01-25 09:56:08 +0100 | [diff] [blame] | 304 | /* no DDR2 Controller */ |
| 305 | #undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1 |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 306 | |
Daniel Hellstrom | e045a4c | 2008-03-26 23:34:47 +0100 | [diff] [blame] | 307 | /* default kernel command line */ |
| 308 | #define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0" |
| 309 | |
| 310 | #endif /* __CONFIG_H */ |