Chen-Yu Tsai | bbce376 | 2020-04-27 14:52:49 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Kever Yang | fc281b7 | 2017-02-23 15:37:50 +0800 | [diff] [blame] | 2 | /* |
Chen-Yu Tsai | bbce376 | 2020-04-27 14:52:49 +0800 | [diff] [blame^] | 3 | * Copyright (c) 2016 Rockchip Electronics Co. Ltd. |
| 4 | * Author: Elaine <zhangqing@rock-chips.com> |
Kever Yang | fc281b7 | 2017-02-23 15:37:50 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H |
| 8 | #define _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H |
| 9 | |
| 10 | /* core clocks */ |
| 11 | #define PLL_APLL 1 |
| 12 | #define PLL_DPLL 2 |
| 13 | #define PLL_CPLL 3 |
| 14 | #define PLL_GPLL 4 |
| 15 | #define PLL_NPLL 5 |
| 16 | #define ARMCLK 6 |
| 17 | |
| 18 | /* sclk gates (special clocks) */ |
| 19 | #define SCLK_RTC32K 30 |
| 20 | #define SCLK_SDMMC_EXT 31 |
| 21 | #define SCLK_SPI 32 |
| 22 | #define SCLK_SDMMC 33 |
| 23 | #define SCLK_SDIO 34 |
| 24 | #define SCLK_EMMC 35 |
| 25 | #define SCLK_TSADC 36 |
| 26 | #define SCLK_SARADC 37 |
| 27 | #define SCLK_UART0 38 |
| 28 | #define SCLK_UART1 39 |
| 29 | #define SCLK_UART2 40 |
| 30 | #define SCLK_I2S0 41 |
| 31 | #define SCLK_I2S1 42 |
| 32 | #define SCLK_I2S2 43 |
| 33 | #define SCLK_I2S1_OUT 44 |
| 34 | #define SCLK_I2S2_OUT 45 |
| 35 | #define SCLK_SPDIF 46 |
| 36 | #define SCLK_TIMER0 47 |
| 37 | #define SCLK_TIMER1 48 |
| 38 | #define SCLK_TIMER2 49 |
| 39 | #define SCLK_TIMER3 50 |
| 40 | #define SCLK_TIMER4 51 |
| 41 | #define SCLK_TIMER5 52 |
| 42 | #define SCLK_WIFI 53 |
| 43 | #define SCLK_CIF_OUT 54 |
| 44 | #define SCLK_I2C0 55 |
| 45 | #define SCLK_I2C1 56 |
| 46 | #define SCLK_I2C2 57 |
| 47 | #define SCLK_I2C3 58 |
| 48 | #define SCLK_CRYPTO 59 |
| 49 | #define SCLK_PWM 60 |
| 50 | #define SCLK_PDM 61 |
| 51 | #define SCLK_EFUSE 62 |
| 52 | #define SCLK_OTP 63 |
| 53 | #define SCLK_DDRCLK 64 |
| 54 | #define SCLK_VDEC_CABAC 65 |
| 55 | #define SCLK_VDEC_CORE 66 |
| 56 | #define SCLK_VENC_DSP 67 |
| 57 | #define SCLK_VENC_CORE 68 |
| 58 | #define SCLK_RGA 69 |
| 59 | #define SCLK_HDMI_SFC 70 |
| 60 | #define SCLK_HDMI_CEC 71 |
| 61 | #define SCLK_USB3_REF 72 |
| 62 | #define SCLK_USB3_SUSPEND 73 |
| 63 | #define SCLK_SDMMC_DRV 74 |
| 64 | #define SCLK_SDIO_DRV 75 |
| 65 | #define SCLK_EMMC_DRV 76 |
| 66 | #define SCLK_SDMMC_EXT_DRV 77 |
| 67 | #define SCLK_SDMMC_SAMPLE 78 |
| 68 | #define SCLK_SDIO_SAMPLE 79 |
| 69 | #define SCLK_EMMC_SAMPLE 80 |
| 70 | #define SCLK_SDMMC_EXT_SAMPLE 81 |
| 71 | #define SCLK_VOP 82 |
| 72 | #define SCLK_MAC2PHY_RXTX 83 |
| 73 | #define SCLK_MAC2PHY_SRC 84 |
| 74 | #define SCLK_MAC2PHY_REF 85 |
| 75 | #define SCLK_MAC2PHY_OUT 86 |
| 76 | #define SCLK_MAC2IO_RX 87 |
| 77 | #define SCLK_MAC2IO_TX 88 |
| 78 | #define SCLK_MAC2IO_REFOUT 89 |
| 79 | #define SCLK_MAC2IO_REF 90 |
| 80 | #define SCLK_MAC2IO_OUT 91 |
| 81 | #define SCLK_TSP 92 |
| 82 | #define SCLK_HSADC_TSP 93 |
| 83 | #define SCLK_USB3PHY_REF 94 |
| 84 | #define SCLK_REF_USB3OTG 95 |
| 85 | #define SCLK_USB3OTG_REF 96 |
| 86 | #define SCLK_USB3OTG_SUSPEND 97 |
| 87 | #define SCLK_REF_USB3OTG_SRC 98 |
| 88 | #define SCLK_MAC2IO_SRC 99 |
David Wu | f01c581 | 2018-01-13 14:02:36 +0800 | [diff] [blame] | 89 | #define SCLK_MAC2IO 100 |
| 90 | #define SCLK_MAC2PHY 101 |
| 91 | #define SCLK_MAC2IO_EXT 102 |
Kever Yang | fc281b7 | 2017-02-23 15:37:50 +0800 | [diff] [blame] | 92 | |
| 93 | /* dclk gates */ |
Chen-Yu Tsai | bbce376 | 2020-04-27 14:52:49 +0800 | [diff] [blame^] | 94 | #define DCLK_LCDC 120 |
| 95 | #define DCLK_HDMIPHY 121 |
| 96 | #define HDMIPHY 122 |
| 97 | #define USB480M 123 |
| 98 | #define DCLK_LCDC_SRC 124 |
Kever Yang | fc281b7 | 2017-02-23 15:37:50 +0800 | [diff] [blame] | 99 | |
| 100 | /* aclk gates */ |
Chen-Yu Tsai | bbce376 | 2020-04-27 14:52:49 +0800 | [diff] [blame^] | 101 | #define ACLK_AXISRAM 130 |
| 102 | #define ACLK_VOP_PRE 131 |
| 103 | #define ACLK_USB3OTG 132 |
| 104 | #define ACLK_RGA_PRE 133 |
| 105 | #define ACLK_DMAC 134 |
| 106 | #define ACLK_GPU 135 |
| 107 | #define ACLK_BUS_PRE 136 |
| 108 | #define ACLK_PERI_PRE 137 |
| 109 | #define ACLK_RKVDEC_PRE 138 |
| 110 | #define ACLK_RKVDEC 139 |
| 111 | #define ACLK_RKVENC 140 |
| 112 | #define ACLK_VPU_PRE 141 |
| 113 | #define ACLK_VIO_PRE 142 |
| 114 | #define ACLK_VPU 143 |
| 115 | #define ACLK_VIO 144 |
| 116 | #define ACLK_VOP 145 |
| 117 | #define ACLK_GMAC 146 |
| 118 | #define ACLK_H265 147 |
| 119 | #define ACLK_H264 148 |
| 120 | #define ACLK_MAC2PHY 149 |
| 121 | #define ACLK_MAC2IO 150 |
| 122 | #define ACLK_DCF 151 |
| 123 | #define ACLK_TSP 152 |
| 124 | #define ACLK_PERI 153 |
| 125 | #define ACLK_RGA 154 |
| 126 | #define ACLK_IEP 155 |
| 127 | #define ACLK_CIF 156 |
| 128 | #define ACLK_HDCP 157 |
Kever Yang | fc281b7 | 2017-02-23 15:37:50 +0800 | [diff] [blame] | 129 | |
| 130 | /* pclk gates */ |
Chen-Yu Tsai | bbce376 | 2020-04-27 14:52:49 +0800 | [diff] [blame^] | 131 | #define PCLK_GPIO0 200 |
| 132 | #define PCLK_GPIO1 201 |
| 133 | #define PCLK_GPIO2 202 |
| 134 | #define PCLK_GPIO3 203 |
| 135 | #define PCLK_GRF 204 |
| 136 | #define PCLK_I2C0 205 |
| 137 | #define PCLK_I2C1 206 |
| 138 | #define PCLK_I2C2 207 |
| 139 | #define PCLK_I2C3 208 |
| 140 | #define PCLK_SPI 209 |
| 141 | #define PCLK_UART0 210 |
| 142 | #define PCLK_UART1 211 |
| 143 | #define PCLK_UART2 212 |
| 144 | #define PCLK_TSADC 213 |
| 145 | #define PCLK_PWM 214 |
| 146 | #define PCLK_TIMER 215 |
| 147 | #define PCLK_BUS_PRE 216 |
| 148 | #define PCLK_PERI_PRE 217 |
| 149 | #define PCLK_HDMI_CTRL 218 |
| 150 | #define PCLK_HDMI_PHY 219 |
| 151 | #define PCLK_GMAC 220 |
| 152 | #define PCLK_H265 221 |
| 153 | #define PCLK_MAC2PHY 222 |
| 154 | #define PCLK_MAC2IO 223 |
| 155 | #define PCLK_USB3PHY_OTG 224 |
| 156 | #define PCLK_USB3PHY_PIPE 225 |
| 157 | #define PCLK_USB3_GRF 226 |
| 158 | #define PCLK_USB2_GRF 227 |
| 159 | #define PCLK_HDMIPHY 228 |
| 160 | #define PCLK_DDR 229 |
| 161 | #define PCLK_PERI 230 |
| 162 | #define PCLK_HDMI 231 |
| 163 | #define PCLK_HDCP 232 |
| 164 | #define PCLK_DCF 233 |
| 165 | #define PCLK_SARADC 234 |
| 166 | #define PCLK_ACODECPHY 235 |
| 167 | #define PCLK_WDT 236 |
Kever Yang | fc281b7 | 2017-02-23 15:37:50 +0800 | [diff] [blame] | 168 | |
| 169 | /* hclk gates */ |
Chen-Yu Tsai | bbce376 | 2020-04-27 14:52:49 +0800 | [diff] [blame^] | 170 | #define HCLK_PERI 308 |
| 171 | #define HCLK_TSP 309 |
| 172 | #define HCLK_GMAC 310 |
| 173 | #define HCLK_I2S0_8CH 311 |
| 174 | #define HCLK_I2S1_8CH 312 |
| 175 | #define HCLK_I2S2_2CH 313 |
| 176 | #define HCLK_SPDIF_8CH 314 |
| 177 | #define HCLK_VOP 315 |
| 178 | #define HCLK_NANDC 316 |
| 179 | #define HCLK_SDMMC 317 |
| 180 | #define HCLK_SDIO 318 |
| 181 | #define HCLK_EMMC 319 |
| 182 | #define HCLK_SDMMC_EXT 320 |
| 183 | #define HCLK_RKVDEC_PRE 321 |
| 184 | #define HCLK_RKVDEC 322 |
| 185 | #define HCLK_RKVENC 323 |
| 186 | #define HCLK_VPU_PRE 324 |
| 187 | #define HCLK_VIO_PRE 325 |
| 188 | #define HCLK_VPU 326 |
| 189 | #define HCLK_BUS_PRE 328 |
| 190 | #define HCLK_PERI_PRE 329 |
| 191 | #define HCLK_H264 330 |
| 192 | #define HCLK_CIF 331 |
| 193 | #define HCLK_OTG_PMU 332 |
| 194 | #define HCLK_OTG 333 |
| 195 | #define HCLK_HOST0 334 |
| 196 | #define HCLK_HOST0_ARB 335 |
| 197 | #define HCLK_CRYPTO_MST 336 |
| 198 | #define HCLK_CRYPTO_SLV 337 |
| 199 | #define HCLK_PDM 338 |
| 200 | #define HCLK_IEP 339 |
| 201 | #define HCLK_RGA 340 |
| 202 | #define HCLK_HDCP 341 |
Kever Yang | fc281b7 | 2017-02-23 15:37:50 +0800 | [diff] [blame] | 203 | |
| 204 | #define CLK_NR_CLKS (HCLK_HDCP + 1) |
| 205 | |
Kever Yang | fc281b7 | 2017-02-23 15:37:50 +0800 | [diff] [blame] | 206 | /* soft-reset indices */ |
| 207 | #define SRST_CORE0_PO 0 |
| 208 | #define SRST_CORE1_PO 1 |
| 209 | #define SRST_CORE2_PO 2 |
| 210 | #define SRST_CORE3_PO 3 |
| 211 | #define SRST_CORE0 4 |
| 212 | #define SRST_CORE1 5 |
| 213 | #define SRST_CORE2 6 |
| 214 | #define SRST_CORE3 7 |
| 215 | #define SRST_CORE0_DBG 8 |
| 216 | #define SRST_CORE1_DBG 9 |
| 217 | #define SRST_CORE2_DBG 10 |
| 218 | #define SRST_CORE3_DBG 11 |
| 219 | #define SRST_TOPDBG 12 |
| 220 | #define SRST_CORE_NIU 13 |
| 221 | #define SRST_STRC_A 14 |
| 222 | #define SRST_L2C 15 |
| 223 | |
| 224 | #define SRST_A53_GIC 18 |
| 225 | #define SRST_DAP 19 |
| 226 | #define SRST_PMU_P 21 |
| 227 | #define SRST_EFUSE 22 |
| 228 | #define SRST_BUSSYS_H 23 |
| 229 | #define SRST_BUSSYS_P 24 |
| 230 | #define SRST_SPDIF 25 |
| 231 | #define SRST_INTMEM 26 |
| 232 | #define SRST_ROM 27 |
| 233 | #define SRST_GPIO0 28 |
| 234 | #define SRST_GPIO1 29 |
| 235 | #define SRST_GPIO2 30 |
| 236 | #define SRST_GPIO3 31 |
| 237 | |
| 238 | #define SRST_I2S0 32 |
| 239 | #define SRST_I2S1 33 |
| 240 | #define SRST_I2S2 34 |
| 241 | #define SRST_I2S0_H 35 |
| 242 | #define SRST_I2S1_H 36 |
| 243 | #define SRST_I2S2_H 37 |
| 244 | #define SRST_UART0 38 |
| 245 | #define SRST_UART1 39 |
| 246 | #define SRST_UART2 40 |
| 247 | #define SRST_UART0_P 41 |
| 248 | #define SRST_UART1_P 42 |
| 249 | #define SRST_UART2_P 43 |
| 250 | #define SRST_I2C0 44 |
| 251 | #define SRST_I2C1 45 |
| 252 | #define SRST_I2C2 46 |
| 253 | #define SRST_I2C3 47 |
| 254 | |
| 255 | #define SRST_I2C0_P 48 |
| 256 | #define SRST_I2C1_P 49 |
| 257 | #define SRST_I2C2_P 50 |
| 258 | #define SRST_I2C3_P 51 |
| 259 | #define SRST_EFUSE_SE_P 52 |
| 260 | #define SRST_EFUSE_NS_P 53 |
| 261 | #define SRST_PWM0 54 |
| 262 | #define SRST_PWM0_P 55 |
| 263 | #define SRST_DMA 56 |
| 264 | #define SRST_TSP_A 57 |
| 265 | #define SRST_TSP_H 58 |
| 266 | #define SRST_TSP 59 |
| 267 | #define SRST_TSP_HSADC 60 |
| 268 | #define SRST_DCF_A 61 |
| 269 | #define SRST_DCF_P 62 |
| 270 | |
| 271 | #define SRST_SCR 64 |
| 272 | #define SRST_SPI 65 |
| 273 | #define SRST_TSADC 66 |
| 274 | #define SRST_TSADC_P 67 |
| 275 | #define SRST_CRYPTO 68 |
| 276 | #define SRST_SGRF 69 |
| 277 | #define SRST_GRF 70 |
| 278 | #define SRST_USB_GRF 71 |
| 279 | #define SRST_TIMER_6CH_P 72 |
| 280 | #define SRST_TIMER0 73 |
| 281 | #define SRST_TIMER1 74 |
| 282 | #define SRST_TIMER2 75 |
| 283 | #define SRST_TIMER3 76 |
| 284 | #define SRST_TIMER4 77 |
| 285 | #define SRST_TIMER5 78 |
| 286 | #define SRST_USB3GRF 79 |
| 287 | |
| 288 | #define SRST_PHYNIU 80 |
| 289 | #define SRST_HDMIPHY 81 |
| 290 | #define SRST_VDAC 82 |
| 291 | #define SRST_ACODEC_p 83 |
| 292 | #define SRST_SARADC 85 |
| 293 | #define SRST_SARADC_P 86 |
| 294 | #define SRST_GRF_DDR 87 |
| 295 | #define SRST_DFIMON 88 |
| 296 | #define SRST_MSCH 89 |
| 297 | #define SRST_DDRMSCH 91 |
| 298 | #define SRST_DDRCTRL 92 |
| 299 | #define SRST_DDRCTRL_P 93 |
| 300 | #define SRST_DDRPHY 94 |
| 301 | #define SRST_DDRPHY_P 95 |
| 302 | |
| 303 | #define SRST_GMAC_NIU_A 96 |
| 304 | #define SRST_GMAC_NIU_P 97 |
| 305 | #define SRST_GMAC2PHY_A 98 |
| 306 | #define SRST_GMAC2IO_A 99 |
| 307 | #define SRST_MACPHY 100 |
| 308 | #define SRST_OTP_PHY 101 |
| 309 | #define SRST_GPU_A 102 |
| 310 | #define SRST_GPU_NIU_A 103 |
| 311 | #define SRST_SDMMCEXT 104 |
| 312 | #define SRST_PERIPH_NIU_A 105 |
| 313 | #define SRST_PERIHP_NIU_H 106 |
| 314 | #define SRST_PERIHP_P 107 |
| 315 | #define SRST_PERIPHSYS_H 108 |
| 316 | #define SRST_MMC0 109 |
| 317 | #define SRST_SDIO 110 |
| 318 | #define SRST_EMMC 111 |
| 319 | |
| 320 | #define SRST_USB2OTG_H 112 |
| 321 | #define SRST_USB2OTG 113 |
| 322 | #define SRST_USB2OTG_ADP 114 |
| 323 | #define SRST_USB2HOST_H 115 |
| 324 | #define SRST_USB2HOST_ARB 116 |
| 325 | #define SRST_USB2HOST_AUX 117 |
| 326 | #define SRST_USB2HOST_EHCIPHY 118 |
| 327 | #define SRST_USB2HOST_UTMI 119 |
| 328 | #define SRST_USB3OTG 120 |
| 329 | #define SRST_USBPOR 121 |
| 330 | #define SRST_USB2OTG_UTMI 122 |
| 331 | #define SRST_USB2HOST_PHY_UTMI 123 |
| 332 | #define SRST_USB3OTG_UTMI 124 |
| 333 | #define SRST_USB3PHY_U2 125 |
| 334 | #define SRST_USB3PHY_U3 126 |
| 335 | #define SRST_USB3PHY_PIPE 127 |
| 336 | |
| 337 | #define SRST_VIO_A 128 |
| 338 | #define SRST_VIO_BUS_H 129 |
| 339 | #define SRST_VIO_H2P_H 130 |
| 340 | #define SRST_VIO_ARBI_H 131 |
| 341 | #define SRST_VOP_NIU_A 132 |
| 342 | #define SRST_VOP_A 133 |
| 343 | #define SRST_VOP_H 134 |
| 344 | #define SRST_VOP_D 135 |
| 345 | #define SRST_RGA 136 |
| 346 | #define SRST_RGA_NIU_A 137 |
| 347 | #define SRST_RGA_A 138 |
| 348 | #define SRST_RGA_H 139 |
| 349 | #define SRST_IEP_A 140 |
| 350 | #define SRST_IEP_H 141 |
| 351 | #define SRST_HDMI 142 |
| 352 | #define SRST_HDMI_P 143 |
| 353 | |
| 354 | #define SRST_HDCP_A 144 |
| 355 | #define SRST_HDCP 145 |
| 356 | #define SRST_HDCP_H 146 |
| 357 | #define SRST_CIF_A 147 |
| 358 | #define SRST_CIF_H 148 |
| 359 | #define SRST_CIF_P 149 |
| 360 | #define SRST_OTP_P 150 |
| 361 | #define SRST_OTP_SBPI 151 |
| 362 | #define SRST_OTP_USER 152 |
| 363 | #define SRST_DDRCTRL_A 153 |
| 364 | #define SRST_DDRSTDY_P 154 |
| 365 | #define SRST_DDRSTDY 155 |
| 366 | #define SRST_PDM_H 156 |
| 367 | #define SRST_PDM 157 |
| 368 | #define SRST_USB3PHY_OTG_P 158 |
| 369 | #define SRST_USB3PHY_PIPE_P 159 |
| 370 | |
| 371 | #define SRST_VCODEC_A 160 |
| 372 | #define SRST_VCODEC_NIU_A 161 |
| 373 | #define SRST_VCODEC_H 162 |
| 374 | #define SRST_VCODEC_NIU_H 163 |
| 375 | #define SRST_VDEC_A 164 |
| 376 | #define SRST_VDEC_NIU_A 165 |
| 377 | #define SRST_VDEC_H 166 |
| 378 | #define SRST_VDEC_NIU_H 167 |
| 379 | #define SRST_VDEC_CORE 168 |
| 380 | #define SRST_VDEC_CABAC 169 |
| 381 | #define SRST_DDRPHYDIV 175 |
| 382 | |
| 383 | #define SRST_RKVENC_NIU_A 176 |
| 384 | #define SRST_RKVENC_NIU_H 177 |
| 385 | #define SRST_RKVENC_H265_A 178 |
| 386 | #define SRST_RKVENC_H265_P 179 |
| 387 | #define SRST_RKVENC_H265_CORE 180 |
| 388 | #define SRST_RKVENC_H265_DSP 181 |
| 389 | #define SRST_RKVENC_H264_A 182 |
| 390 | #define SRST_RKVENC_H264_H 183 |
| 391 | #define SRST_RKVENC_INTMEM 184 |
| 392 | |
| 393 | #endif |