| masakazu.mochizuki.wd@hitachi.com | 9d0e937 | 2016-04-12 17:11:41 +0900 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/include/asm/arch-rmobile/r8a7792.h |
| 3 | * |
| 4 | * Copyright (C) 2016 Renesas Electronics Corporation |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0 |
| 7 | */ |
| 8 | |
| 9 | #ifndef __ASM_ARCH_R8A7792_H |
| 10 | #define __ASM_ARCH_R8A7792_H |
| 11 | |
| 12 | #include "rcar-base.h" |
| 13 | |
| 14 | /* SH-I2C */ |
| 15 | #define CONFIG_SYS_I2C_SH_BASE2 0xE6520000 |
| 16 | #define CONFIG_SYS_I2C_SH_BASE3 0xE60B0000 |
| 17 | |
| 18 | /* Module stop control/status register bits */ |
| 19 | #define MSTP0_BITS 0x00400801 |
| 20 | #define MSTP1_BITS 0x9B6F987F |
| 21 | #define MSTP2_BITS 0x108CE100 |
| 22 | #define MSTP3_BITS 0x20004010 |
| 23 | #define MSTP4_BITS 0x80000184 |
| 24 | #define MSTP5_BITS 0x44C00004 |
| 25 | #define MSTP7_BITS 0x01BF0000 |
| 26 | #define MSTP8_BITS 0x1FE01FB0 |
| 27 | #define MSTP9_BITS 0xFE2BFFB2 |
| 28 | #define MSTP10_BITS 0x00001820 |
| 29 | #define MSTP11_BITS 0x00000008 |
| 30 | |
| 31 | /* SDHI */ |
| 32 | #define CONFIG_SYS_SH_SDHI_NR_CHANNEL 1 |
| 33 | |
| 34 | #endif /* __ASM_ARCH_R8A7792_H */ |