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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Pali Rohár248ef0a2012-10-29 07:54:01 +00002/*
3 * (C) Copyright 2011-2012
Pali Rohár10a953d2020-04-01 00:35:08 +02004 * Pali Rohár <pali@kernel.org>
Pali Rohár248ef0a2012-10-29 07:54:01 +00005 *
6 * (C) Copyright 2010
7 * Alistair Buxton <a.j.buxton@gmail.com>
8 *
9 * Derived from Beagle Board code:
10 * (C) Copyright 2006-2008
11 * Texas Instruments.
12 * Richard Woodruff <r-woodruff2@ti.com>
13 * Syed Mohammed Khasim <x0khasim@ti.com>
14 *
15 * Configuration settings for the Nokia RX-51 aka N900.
Pali Rohár248ef0a2012-10-29 07:54:01 +000016 */
17
18#ifndef __CONFIG_H
19#define __CONFIG_H
20
21/*
22 * High Level Configuration Options
23 */
Pali Rohár248ef0a2012-10-29 07:54:01 +000024
Pali Rohár248ef0a2012-10-29 07:54:01 +000025#include <asm/arch/cpu.h> /* get chip and board defs */
Nishanth Menonfa96c962015-03-09 17:12:04 -050026#include <asm/arch/omap.h>
Pali Rohár248ef0a2012-10-29 07:54:01 +000027#include <asm/arch/mem.h>
28#include <linux/stringify.h>
29
Pali Rohár248ef0a2012-10-29 07:54:01 +000030/* Clock Defines */
31#define V_OSCK 26000000 /* Clock output from T2 */
32#define V_SCLK (V_OSCK >> 1)
33
Pali Rohár248ef0a2012-10-29 07:54:01 +000034/*
35 * Hardware drivers
36 */
37
38/*
39 * NS16550 Configuration
40 */
41#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
42
Tom Rinidf6a2152022-11-16 13:10:28 -050043#define CFG_SYS_NS16550_CLK V_NS16550_CLK
Pali Rohár248ef0a2012-10-29 07:54:01 +000044
45/*
46 * select serial console configuration
47 */
Tom Rinidf6a2152022-11-16 13:10:28 -050048#define CFG_SYS_NS16550_COM3 OMAP34XX_UART3
Pali Rohár248ef0a2012-10-29 07:54:01 +000049
Pali Rohár248ef0a2012-10-29 07:54:01 +000050#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 }
Pali Rohár248ef0a2012-10-29 07:54:01 +000051
Pali Rohár248ef0a2012-10-29 07:54:01 +000052/* USB device configuration */
53#define CONFIG_USB_DEVICE
Pali Rohárbba0bba2021-02-20 11:50:15 +010054#define CONFIG_USB_TTY
Pali Rohár248ef0a2012-10-29 07:54:01 +000055#define CONFIG_USBD_VENDORID 0x0421
Pali Rohárbba0bba2021-02-20 11:50:15 +010056#define CONFIG_USBD_PRODUCTID_CDCACM 0x01c8
57#define CONFIG_USBD_PRODUCTID_GSERIAL 0x01c8
Pali Rohár248ef0a2012-10-29 07:54:01 +000058#define CONFIG_USBD_MANUFACTURER "Nokia"
Pali Rohárbba0bba2021-02-20 11:50:15 +010059#define CONFIG_USBD_PRODUCT_NAME "N900 (U-Boot)"
Pali Rohár248ef0a2012-10-29 07:54:01 +000060
Pali Rohár248ef0a2012-10-29 07:54:01 +000061#define GPIO_SLIDE 71
62
63/*
64 * Board ONENAND Info.
65 */
66
Pali Rohár248ef0a2012-10-29 07:54:01 +000067#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
Pali Rohár248ef0a2012-10-29 07:54:01 +000068
Pali Rohár248ef0a2012-10-29 07:54:01 +000069/* Environment information */
Pali Rohár248ef0a2012-10-29 07:54:01 +000070#define CONFIG_EXTRA_ENV_SETTINGS \
Pali Rohár248ef0a2012-10-29 07:54:01 +000071 "usbtty=cdc_acm\0" \
Pali Rohár54a30142022-02-03 19:38:50 +010072 "stdin=usbtty,serial,keyboard\0" \
Pali Rohár1d701a52022-03-09 20:46:01 +010073 "stdout=usbtty,serial,vidconsole\0" \
74 "stderr=usbtty,serial,vidconsole\0" \
Pali Rohár248ef0a2012-10-29 07:54:01 +000075 "slide=gpio input " __stringify(GPIO_SLIDE) "\0" \
76 "switchmmc=mmc dev ${mmcnum}\0" \
77 "kernaddr=0x82008000\0" \
78 "initrdaddr=0x84008000\0" \
79 "scriptaddr=0x86008000\0" \
Pali Rohár0dff39f2022-11-20 17:56:28 +010080 "fileloadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
Pali Rohár248ef0a2012-10-29 07:54:01 +000081 "fileload=${mmctype}load mmc ${mmcnum}:${mmcpart} " \
Pali Rohár0dff39f2022-11-20 17:56:28 +010082 "${fileloadaddr} ${mmcfile}\0" \
83 "kernload=setenv fileloadaddr ${kernaddr};" \
Pali Rohár248ef0a2012-10-29 07:54:01 +000084 "setenv mmcfile ${mmckernfile};" \
85 "run fileload\0" \
Pali Rohár0dff39f2022-11-20 17:56:28 +010086 "initrdload=setenv fileloadaddr ${initrdaddr};" \
Pali Rohár248ef0a2012-10-29 07:54:01 +000087 "setenv mmcfile ${mmcinitrdfile};" \
88 "run fileload\0" \
Pali Rohár0dff39f2022-11-20 17:56:28 +010089 "scriptload=setenv fileloadaddr ${scriptaddr};" \
Pali Rohár248ef0a2012-10-29 07:54:01 +000090 "setenv mmcfile ${mmcscriptfile};" \
91 "run fileload\0" \
92 "scriptboot=echo Running ${mmcscriptfile} from mmc " \
93 "${mmcnum}:${mmcpart} ...; source ${scriptaddr}\0" \
94 "kernboot=echo Booting ${mmckernfile} from mmc " \
Pali Rohár0a8825c2021-06-18 15:27:03 +020095 "${mmcnum}:${mmcpart} ...; bootm ${kernaddr} || " \
96 "bootz ${kernaddr}\0" \
Pali Rohár248ef0a2012-10-29 07:54:01 +000097 "kerninitrdboot=echo Booting ${mmckernfile} ${mmcinitrdfile} from mmc "\
Pali Rohár0a8825c2021-06-18 15:27:03 +020098 "${mmcnum}:${mmcpart} ...; bootm ${kernaddr} ${initrdaddr} || " \
99 "bootz ${kernaddr} ${initrdaddr}\0" \
Pali Rohár248ef0a2012-10-29 07:54:01 +0000100 "attachboot=echo Booting attached kernel image ...;" \
101 "setenv setup_omap_atag 1;" \
Pali Rohár0a8825c2021-06-18 15:27:03 +0200102 "bootm ${attkernaddr} || bootz ${attkernaddr};" \
Pali Rohár248ef0a2012-10-29 07:54:01 +0000103 "setenv setup_omap_atag\0" \
Pali Rohár5e0f5132021-06-18 15:27:04 +0200104 "trymmcscriptboot=run switchmmc && run scriptload && run scriptboot\0" \
105 "trymmckernboot=run switchmmc && run kernload && run kernboot\0" \
106 "trymmckerninitrdboot=run switchmmc && run initrdload && " \
107 "run kernload && run kerninitrdboot\0" \
Pali Rohár248ef0a2012-10-29 07:54:01 +0000108 "trymmcpartboot=setenv mmcscriptfile boot.scr; run trymmcscriptboot;" \
Pali Rohár0a8825c2021-06-18 15:27:03 +0200109 "setenv mmckernfile uImage; run trymmckernboot;" \
110 "setenv mmckernfile zImage; run trymmckernboot\0" \
Pali Rohár248ef0a2012-10-29 07:54:01 +0000111 "trymmcallpartboot=setenv mmcpart 1; run trymmcpartboot;" \
112 "setenv mmcpart 2; run trymmcpartboot;" \
113 "setenv mmcpart 3; run trymmcpartboot;" \
114 "setenv mmcpart 4; run trymmcpartboot\0" \
115 "trymmcboot=if run switchmmc; then " \
116 "setenv mmctype fat;" \
117 "run trymmcallpartboot;" \
Pali Rohár248ef0a2012-10-29 07:54:01 +0000118 "setenv mmctype ext4;" \
119 "run trymmcallpartboot;" \
120 "fi\0" \
121 "emmcboot=setenv mmcnum 1; run trymmcboot\0" \
122 "sdboot=setenv mmcnum 0; run trymmcboot\0" \
Pali Rohár5e0f5132021-06-18 15:27:04 +0200123 "trymmcbootmenu=setenv mmctype fat && run trymmcscriptboot || " \
124 "setenv mmctype ext4 && run trymmcscriptboot\0" \
125 "preboot=setenv mmcpart 1; setenv mmcscriptfile bootmenu.scr;" \
126 "setenv mmcnum 0 && run trymmcbootmenu || " \
127 "setenv mmcnum 1 && run trymmcbootmenu;" \
Pali Rohár6f52aee2020-04-01 00:35:11 +0200128 "if run slide; then true; else " \
129 "setenv bootmenu_delay 0;" \
130 "setenv bootdelay 0;" \
131 "fi\0" \
Pali Rohár13eb3e42013-03-07 05:15:19 +0000132 "menucmd=bootmenu\0" \
133 "bootmenu_0=Attached kernel=run attachboot\0" \
134 "bootmenu_1=Internal eMMC=run emmcboot\0" \
135 "bootmenu_2=External SD card=run sdboot\0" \
136 "bootmenu_3=U-Boot boot order=boot\0" \
137 "bootmenu_delay=30\0" \
Pali Rohár248ef0a2012-10-29 07:54:01 +0000138 ""
139
Pali Rohár13eb3e42013-03-07 05:15:19 +0000140#define CONFIG_POSTBOOTMENU \
141 "echo;" \
Pali Rohár248ef0a2012-10-29 07:54:01 +0000142 "echo Extra commands:;" \
Pali Rohár248ef0a2012-10-29 07:54:01 +0000143 "echo run sdboot - Boot from SD card slot.;" \
144 "echo run emmcboot - Boot internal eMMC memory.;" \
145 "echo run attachboot - Boot attached kernel image.;" \
146 "echo"
147
Pali Rohár248ef0a2012-10-29 07:54:01 +0000148/*
149 * OMAP3 has 12 GP timers, they can be driven by the system clock
150 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
151 * This rate is divided by a local divisor.
152 */
153#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
Pali Rohár248ef0a2012-10-29 07:54:01 +0000154
155/*
Pali Rohár248ef0a2012-10-29 07:54:01 +0000156 * Physical Memory Map
157 */
Pali Rohár248ef0a2012-10-29 07:54:01 +0000158#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
159
160/*
161 * FLASH and environment organization
162 */
163
Tom Rinibb4dd962022-11-16 13:10:37 -0500164#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
Pali Rohár248ef0a2012-10-29 07:54:01 +0000165#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
166#define CONFIG_SYS_INIT_RAM_SIZE 0x800
Pali Rohár248ef0a2012-10-29 07:54:01 +0000167
168/*
169 * Attached kernel image
170 */
171
172#define SDRAM_SIZE 0x10000000 /* 256 MB */
Tom Rinibb4dd962022-11-16 13:10:37 -0500173#define SDRAM_END (CFG_SYS_SDRAM_BASE + SDRAM_SIZE)
Pali Rohár248ef0a2012-10-29 07:54:01 +0000174
175#define IMAGE_MAXSIZE 0x1FF800 /* 2 MB - 2 kB */
176#define KERNEL_OFFSET 0x40000 /* 256 kB */
177#define KERNEL_MAXSIZE (IMAGE_MAXSIZE-KERNEL_OFFSET)
178#define KERNEL_ADDRESS (SDRAM_END-KERNEL_MAXSIZE)
179
180/* Reserve protected RAM for attached kernel */
181#define CONFIG_PRAM ((KERNEL_MAXSIZE >> 10)+1)
182
183#endif /* __CONFIG_H */