Paweł Jarosz | df645ef | 2022-04-16 17:09:41 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause |
| 2 | /* |
| 3 | * (C) Copyright 2015 Google, Inc |
| 4 | * Copyright 2014 Rockchip Inc. |
| 5 | * |
| 6 | * Adapted from the very similar rk3188 ddr init. |
| 7 | */ |
| 8 | |
| 9 | #include <common.h> |
| 10 | #include <clk.h> |
| 11 | #include <dm.h> |
| 12 | #include <dt-structs.h> |
| 13 | #include <errno.h> |
| 14 | #include <hang.h> |
| 15 | #include <init.h> |
| 16 | #include <log.h> |
| 17 | #include <ram.h> |
| 18 | #include <regmap.h> |
| 19 | #include <syscon.h> |
| 20 | #include <asm/io.h> |
| 21 | #include <asm/arch-rockchip/clock.h> |
| 22 | #include <asm/arch-rockchip/cru_rk3066.h> |
| 23 | #include <asm/arch-rockchip/ddr_rk3188.h> |
| 24 | #include <asm/arch-rockchip/grf_rk3066.h> |
| 25 | #include <asm/arch-rockchip/hardware.h> |
| 26 | #include <asm/arch-rockchip/pmu_rk3188.h> |
| 27 | #include <asm/arch-rockchip/sdram_rk3288.h> |
| 28 | #include <asm/arch-rockchip/sdram.h> |
| 29 | #include <linux/delay.h> |
| 30 | #include <linux/err.h> |
| 31 | |
| 32 | struct rk3066_dmc_chan_info { |
| 33 | struct rk3288_ddr_pctl *pctl; |
| 34 | struct rk3288_ddr_publ *publ; |
| 35 | struct rk3188_msch *msch; |
| 36 | }; |
| 37 | |
| 38 | struct rk3066_dmc_dram_info { |
| 39 | struct rk3066_dmc_chan_info chan[1]; |
| 40 | struct ram_info info; |
| 41 | struct clk ddr_clk; |
| 42 | struct rk3066_cru *cru; |
| 43 | struct rk3066_grf *grf; |
| 44 | struct rk3066_sgrf *sgrf; |
| 45 | struct rk3188_pmu *pmu; |
| 46 | }; |
| 47 | |
| 48 | struct rk3066_dmc_sdram_params { |
| 49 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
| 50 | struct dtd_rockchip_rk3066_dmc of_plat; |
| 51 | #endif |
| 52 | struct rk3288_sdram_channel ch[2]; |
| 53 | struct rk3288_sdram_pctl_timing pctl_timing; |
| 54 | struct rk3288_sdram_phy_timing phy_timing; |
| 55 | struct rk3288_base_params base; |
| 56 | int num_channels; |
| 57 | struct regmap *map; |
| 58 | }; |
| 59 | |
| 60 | const int rk3066_dmc_ddrconf_table[] = { |
| 61 | /* |
| 62 | * [5:4] row(13+n) |
| 63 | * [1:0] col(9+n), assume bw=2 |
| 64 | * row col,bw |
| 65 | */ |
| 66 | 0, |
| 67 | (2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT, |
| 68 | (1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT, |
| 69 | (0 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT, |
| 70 | (2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT, |
| 71 | (1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT, |
| 72 | (0 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT, |
| 73 | (1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT, |
| 74 | (0 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT, |
| 75 | 0, |
| 76 | 0, |
| 77 | 0, |
| 78 | 0, |
| 79 | 0, |
| 80 | 0, |
| 81 | 0, |
| 82 | }; |
| 83 | |
| 84 | #define TEST_PATTERN 0x5aa5f00f |
| 85 | #define DQS_GATE_TRAINING_ERROR_RANK0 BIT(4) |
| 86 | #define DQS_GATE_TRAINING_ERROR_RANK1 BIT(5) |
| 87 | |
| 88 | static void rk3066_dmc_copy_to_reg(u32 *dest, const u32 *src, u32 n) |
| 89 | { |
| 90 | int i; |
| 91 | |
| 92 | for (i = 0; i < n / sizeof(u32); i++) { |
| 93 | writel(*src, dest); |
| 94 | src++; |
| 95 | dest++; |
| 96 | } |
| 97 | } |
| 98 | |
| 99 | static void rk3066_dmc_ddr_reset(struct rk3066_cru *cru, u32 ch, u32 ctl, u32 phy) |
| 100 | { |
| 101 | u32 phy_ctl_srstn_shift = 13; |
| 102 | u32 ctl_psrstn_shift = 11; |
| 103 | u32 ctl_srstn_shift = 10; |
| 104 | u32 phy_psrstn_shift = 9; |
| 105 | u32 phy_srstn_shift = 8; |
| 106 | |
| 107 | rk_clrsetreg(&cru->cru_softrst_con[5], |
| 108 | 1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift | |
| 109 | 1 << ctl_srstn_shift | 1 << phy_psrstn_shift | |
| 110 | 1 << phy_srstn_shift, |
| 111 | phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift | |
| 112 | ctl << ctl_srstn_shift | phy << phy_psrstn_shift | |
| 113 | phy << phy_srstn_shift); |
| 114 | } |
| 115 | |
| 116 | static void rk3066_dmc_ddr_phy_ctl_reset(struct rk3066_cru *cru, u32 ch, u32 n) |
| 117 | { |
| 118 | u32 phy_ctl_srstn_shift = 13; |
| 119 | |
| 120 | rk_clrsetreg(&cru->cru_softrst_con[5], |
| 121 | 1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift); |
| 122 | } |
| 123 | |
| 124 | static void rk3066_dmc_phy_pctrl_reset(struct rk3066_cru *cru, |
| 125 | struct rk3288_ddr_publ *publ, |
| 126 | int channel) |
| 127 | { |
| 128 | int i; |
| 129 | |
| 130 | rk3066_dmc_ddr_reset(cru, channel, 1, 1); |
| 131 | udelay(1); |
| 132 | clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); |
| 133 | for (i = 0; i < 4; i++) |
| 134 | clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); |
| 135 | |
| 136 | udelay(10); |
| 137 | setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); |
| 138 | for (i = 0; i < 4; i++) |
| 139 | setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); |
| 140 | |
| 141 | udelay(10); |
| 142 | rk3066_dmc_ddr_reset(cru, channel, 1, 0); |
| 143 | udelay(10); |
| 144 | rk3066_dmc_ddr_reset(cru, channel, 0, 0); |
| 145 | udelay(10); |
| 146 | } |
| 147 | |
| 148 | static void rk3066_dmc_phy_dll_bypass_set(struct rk3288_ddr_publ *publ, u32 freq) |
| 149 | { |
| 150 | int i; |
| 151 | |
| 152 | if (freq <= 250000000) { |
| 153 | if (freq <= 150000000) |
| 154 | clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); |
| 155 | else |
| 156 | setbits_le32(&publ->dllgcr, SBIAS_BYPASS); |
| 157 | setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); |
| 158 | for (i = 0; i < 4; i++) |
| 159 | setbits_le32(&publ->datx8[i].dxdllcr, |
| 160 | DXDLLCR_DLLDIS); |
| 161 | |
| 162 | setbits_le32(&publ->pir, PIR_DLLBYP); |
| 163 | } else { |
| 164 | clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); |
| 165 | clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); |
| 166 | for (i = 0; i < 4; i++) { |
| 167 | clrbits_le32(&publ->datx8[i].dxdllcr, |
| 168 | DXDLLCR_DLLDIS); |
| 169 | } |
| 170 | |
| 171 | clrbits_le32(&publ->pir, PIR_DLLBYP); |
| 172 | } |
| 173 | } |
| 174 | |
| 175 | static void rk3066_dmc_dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype) |
| 176 | { |
| 177 | writel(DFI_INIT_START, &pctl->dfistcfg0); |
| 178 | writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, |
| 179 | &pctl->dfistcfg1); |
| 180 | writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); |
| 181 | writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN, |
| 182 | &pctl->dfilpcfg0); |
| 183 | |
| 184 | writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay); |
| 185 | writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata); |
| 186 | writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat); |
| 187 | writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis); |
| 188 | writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken); |
| 189 | writel(1, &pctl->dfitphyupdtype0); |
| 190 | |
| 191 | /* CS0 and CS1 write ODT enable. */ |
| 192 | writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), |
| 193 | &pctl->dfiodtcfg); |
| 194 | /* Write ODT length. */ |
| 195 | writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1); |
| 196 | /* Disable phyupd and ctrlupd. */ |
| 197 | writel(0, &pctl->dfiupdcfg); |
| 198 | } |
| 199 | |
| 200 | static void rk3066_dmc_ddr_set_ddr3_mode(struct rk3066_grf *grf, uint channel, |
| 201 | bool ddr3_mode) |
| 202 | { |
| 203 | uint mask, val; |
| 204 | |
| 205 | mask = MSCH4_MAINDDR3_MASK << MSCH4_MAINDDR3_SHIFT; |
| 206 | val = ddr3_mode << MSCH4_MAINDDR3_SHIFT; |
| 207 | rk_clrsetreg(&grf->soc_con2, mask, val); |
| 208 | } |
| 209 | |
| 210 | static void rk3066_dmc_ddr_rank_2_row15en(struct rk3066_grf *grf, bool enable) |
| 211 | { |
| 212 | uint mask, val; |
| 213 | |
| 214 | mask = RANK_TO_ROW15_EN_MASK << RANK_TO_ROW15_EN_SHIFT; |
| 215 | val = enable << RANK_TO_ROW15_EN_SHIFT; |
| 216 | rk_clrsetreg(&grf->soc_con2, mask, val); |
| 217 | } |
| 218 | |
| 219 | static void rk3066_dmc_pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl, |
| 220 | struct rk3066_dmc_sdram_params *sdram_params, |
| 221 | struct rk3066_grf *grf) |
| 222 | { |
| 223 | rk3066_dmc_copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, |
| 224 | sizeof(sdram_params->pctl_timing)); |
| 225 | switch (sdram_params->base.dramtype) { |
| 226 | case DDR3: |
| 227 | if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) { |
| 228 | writel(sdram_params->pctl_timing.tcl - 3, |
| 229 | &pctl->dfitrddataen); |
| 230 | } else { |
| 231 | writel(sdram_params->pctl_timing.tcl - 2, |
| 232 | &pctl->dfitrddataen); |
| 233 | } |
| 234 | writel(sdram_params->pctl_timing.tcwl - 1, |
| 235 | &pctl->dfitphywrlat); |
| 236 | writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN | |
| 237 | DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW | |
| 238 | 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT, |
| 239 | &pctl->mcfg); |
| 240 | rk3066_dmc_ddr_set_ddr3_mode(grf, channel, true); |
| 241 | break; |
| 242 | } |
| 243 | |
| 244 | setbits_le32(&pctl->scfg, 1); |
| 245 | } |
| 246 | |
| 247 | static void rk3066_dmc_phy_cfg(const struct rk3066_dmc_chan_info *chan, int channel, |
| 248 | struct rk3066_dmc_sdram_params *sdram_params) |
| 249 | { |
| 250 | struct rk3288_ddr_publ *publ = chan->publ; |
| 251 | struct rk3188_msch *msch = chan->msch; |
| 252 | uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000; |
| 253 | u32 dinit2; |
| 254 | int i; |
| 255 | |
| 256 | dinit2 = DIV_ROUND_UP(ddr_freq_mhz * 200000, 1000); |
| 257 | /* Set DDR PHY timing. */ |
| 258 | rk3066_dmc_copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0, |
| 259 | sizeof(sdram_params->phy_timing)); |
| 260 | writel(sdram_params->base.noc_timing, &msch->ddrtiming); |
| 261 | writel(0x3f, &msch->readlatency); |
| 262 | writel(DIV_ROUND_UP(ddr_freq_mhz * 5120, 1000) << PRT_DLLLOCK_SHIFT | |
| 263 | DIV_ROUND_UP(ddr_freq_mhz * 50, 1000) << PRT_DLLSRST_SHIFT | |
| 264 | 8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]); |
| 265 | writel(DIV_ROUND_UP(ddr_freq_mhz * 500000, 1000) << PRT_DINIT0_SHIFT | |
| 266 | DIV_ROUND_UP(ddr_freq_mhz * 400, 1000) << PRT_DINIT1_SHIFT, |
| 267 | &publ->ptr[1]); |
| 268 | writel(min(dinit2, 0x1ffffU) << PRT_DINIT2_SHIFT | |
| 269 | DIV_ROUND_UP(ddr_freq_mhz * 1000, 1000) << PRT_DINIT3_SHIFT, |
| 270 | &publ->ptr[2]); |
| 271 | |
| 272 | switch (sdram_params->base.dramtype) { |
| 273 | case DDR3: |
| 274 | clrbits_le32(&publ->pgcr, 0x1f); |
| 275 | clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT, |
| 276 | DDRMD_DDR3 << DDRMD_SHIFT); |
| 277 | break; |
| 278 | } |
| 279 | if (sdram_params->base.odt) { |
| 280 | /* Enable dynamic RTT. */ |
| 281 | for (i = 0; i < 4; i++) |
| 282 | setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); |
| 283 | } else { |
| 284 | /* Disable dynamic RTT. */ |
| 285 | for (i = 0; i < 4; i++) |
| 286 | clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); |
| 287 | } |
| 288 | } |
| 289 | |
| 290 | static void rk3066_dmc_phy_init(struct rk3288_ddr_publ *publ) |
| 291 | { |
| 292 | setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST |
| 293 | | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR); |
| 294 | udelay(1); |
| 295 | while ((readl(&publ->pgsr) & |
| 296 | (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) != |
| 297 | (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) |
| 298 | ; |
| 299 | } |
| 300 | |
| 301 | static void rk3066_dmc_send_command(struct rk3288_ddr_pctl *pctl, u32 rank, |
| 302 | u32 cmd, u32 arg) |
| 303 | { |
| 304 | writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); |
| 305 | udelay(1); |
| 306 | while (readl(&pctl->mcmd) & START_CMD) |
| 307 | ; |
| 308 | } |
| 309 | |
| 310 | static inline void rk3066_dmc_send_command_op(struct rk3288_ddr_pctl *pctl, |
| 311 | u32 rank, u32 cmd, u32 ma, u32 op) |
| 312 | { |
| 313 | rk3066_dmc_send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT | |
| 314 | (op & LPDDR2_OP_MASK) << LPDDR2_OP_SHIFT); |
| 315 | } |
| 316 | |
| 317 | static void rk3066_dmc_memory_init(struct rk3288_ddr_publ *publ, |
| 318 | u32 dramtype) |
| 319 | { |
| 320 | setbits_le32(&publ->pir, |
| 321 | (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP |
| 322 | | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC |
| 323 | | (dramtype == DDR3 ? PIR_DRAMRST : 0))); |
| 324 | udelay(1); |
| 325 | while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE)) |
| 326 | != (PGSR_IDONE | PGSR_DLDONE)) |
| 327 | ; |
| 328 | } |
| 329 | |
| 330 | static void rk3066_dmc_move_to_config_state(struct rk3288_ddr_publ *publ, |
| 331 | struct rk3288_ddr_pctl *pctl) |
| 332 | { |
| 333 | unsigned int state; |
| 334 | |
| 335 | while (1) { |
| 336 | state = readl(&pctl->stat) & PCTL_STAT_MSK; |
| 337 | |
| 338 | switch (state) { |
| 339 | case LOW_POWER: |
| 340 | writel(WAKEUP_STATE, &pctl->sctl); |
| 341 | while ((readl(&pctl->stat) & PCTL_STAT_MSK) |
| 342 | != ACCESS) |
| 343 | ; |
| 344 | /* Wait DLL lock. */ |
| 345 | while ((readl(&publ->pgsr) & PGSR_DLDONE) |
| 346 | != PGSR_DLDONE) |
| 347 | ; |
| 348 | /* |
| 349 | * If at low power state we need to wakeup first |
| 350 | * and then enter the config. |
| 351 | */ |
| 352 | fallthrough; |
| 353 | case ACCESS: |
| 354 | fallthrough; |
| 355 | case INIT_MEM: |
| 356 | writel(CFG_STATE, &pctl->sctl); |
| 357 | while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) |
| 358 | ; |
| 359 | break; |
| 360 | case CONFIG: |
| 361 | return; |
| 362 | default: |
| 363 | break; |
| 364 | } |
| 365 | } |
| 366 | } |
| 367 | |
| 368 | static void rk3066_dmc_set_bandwidth_ratio(const struct rk3066_dmc_chan_info *chan, int channel, |
| 369 | u32 n, struct rk3066_grf *grf) |
| 370 | { |
| 371 | struct rk3288_ddr_pctl *pctl = chan->pctl; |
| 372 | struct rk3288_ddr_publ *publ = chan->publ; |
| 373 | struct rk3188_msch *msch = chan->msch; |
| 374 | |
| 375 | if (n == 1) { |
| 376 | setbits_le32(&pctl->ppcfg, 1); |
| 377 | setbits_le32(&msch->ddrtiming, 1 << 31); |
| 378 | /* Data byte disable. */ |
| 379 | clrbits_le32(&publ->datx8[2].dxgcr, 1); |
| 380 | clrbits_le32(&publ->datx8[3].dxgcr, 1); |
| 381 | /* Disable DLL. */ |
| 382 | setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); |
| 383 | setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); |
| 384 | } else { |
| 385 | clrbits_le32(&pctl->ppcfg, 1); |
| 386 | clrbits_le32(&msch->ddrtiming, 1 << 31); |
| 387 | /* Data byte enable.*/ |
| 388 | setbits_le32(&publ->datx8[2].dxgcr, 1); |
| 389 | setbits_le32(&publ->datx8[3].dxgcr, 1); |
| 390 | |
| 391 | /* Enable DLL. */ |
| 392 | clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); |
| 393 | clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); |
| 394 | /* Reset DLL. */ |
| 395 | clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); |
| 396 | clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); |
| 397 | udelay(10); |
| 398 | setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); |
| 399 | setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); |
| 400 | } |
| 401 | setbits_le32(&pctl->dfistcfg0, 1 << 2); |
| 402 | } |
| 403 | |
| 404 | static int rk3066_dmc_data_training(const struct rk3066_dmc_chan_info *chan, int channel, |
| 405 | struct rk3066_dmc_sdram_params *sdram_params) |
| 406 | { |
| 407 | unsigned int j; |
| 408 | int ret = 0; |
| 409 | u32 rank; |
| 410 | int i; |
| 411 | u32 step[2] = { PIR_QSTRN, PIR_RVTRN }; |
| 412 | struct rk3288_ddr_publ *publ = chan->publ; |
| 413 | struct rk3288_ddr_pctl *pctl = chan->pctl; |
| 414 | |
| 415 | /* Disable auto refresh. */ |
| 416 | writel(0, &pctl->trefi); |
| 417 | |
| 418 | if (sdram_params->base.dramtype != LPDDR3) |
| 419 | setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); |
| 420 | rank = sdram_params->ch[channel].rank | 1; |
| 421 | for (j = 0; j < ARRAY_SIZE(step); j++) { |
| 422 | /* |
| 423 | * Trigger QSTRN and RVTRN. |
| 424 | * Clear DTDONE status. |
| 425 | */ |
| 426 | setbits_le32(&publ->pir, PIR_CLRSR); |
| 427 | |
| 428 | /* Trigger DTT. */ |
| 429 | setbits_le32(&publ->pir, |
| 430 | PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP | |
| 431 | PIR_CLRSR); |
| 432 | udelay(1); |
| 433 | /* Wait echo byte DTDONE. */ |
| 434 | while ((readl(&publ->datx8[0].dxgsr[0]) & rank) |
| 435 | != rank) |
| 436 | ; |
| 437 | while ((readl(&publ->datx8[1].dxgsr[0]) & rank) |
| 438 | != rank) |
| 439 | ; |
| 440 | if (!(readl(&pctl->ppcfg) & 1)) { |
| 441 | while ((readl(&publ->datx8[2].dxgsr[0]) |
| 442 | & rank) != rank) |
| 443 | ; |
| 444 | while ((readl(&publ->datx8[3].dxgsr[0]) |
| 445 | & rank) != rank) |
| 446 | ; |
| 447 | } |
| 448 | if (readl(&publ->pgsr) & |
| 449 | (PGSR_DTERR | PGSR_RVERR | PGSR_RVEIRR)) { |
| 450 | ret = -1; |
| 451 | break; |
| 452 | } |
| 453 | } |
| 454 | /* Send some auto refresh to complement the lost while DTT. */ |
| 455 | for (i = 0; i < (rank > 1 ? 8 : 4); i++) |
| 456 | rk3066_dmc_send_command(pctl, rank, REF_CMD, 0); |
| 457 | |
| 458 | if (sdram_params->base.dramtype != LPDDR3) |
| 459 | clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); |
| 460 | |
| 461 | /* Resume auto refresh. */ |
| 462 | writel(sdram_params->pctl_timing.trefi, &pctl->trefi); |
| 463 | |
| 464 | return ret; |
| 465 | } |
| 466 | |
| 467 | static void rk3066_dmc_move_to_access_state(const struct rk3066_dmc_chan_info *chan) |
| 468 | { |
| 469 | struct rk3288_ddr_publ *publ = chan->publ; |
| 470 | struct rk3288_ddr_pctl *pctl = chan->pctl; |
| 471 | unsigned int state; |
| 472 | |
| 473 | while (1) { |
| 474 | state = readl(&pctl->stat) & PCTL_STAT_MSK; |
| 475 | |
| 476 | switch (state) { |
| 477 | case LOW_POWER: |
| 478 | if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) & |
| 479 | LP_TRIG_MASK) == 1) |
| 480 | return; |
| 481 | |
| 482 | writel(WAKEUP_STATE, &pctl->sctl); |
| 483 | while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS) |
| 484 | ; |
| 485 | /* Wait DLL lock. */ |
| 486 | while ((readl(&publ->pgsr) & PGSR_DLDONE) |
| 487 | != PGSR_DLDONE) |
| 488 | ; |
| 489 | break; |
| 490 | case INIT_MEM: |
| 491 | writel(CFG_STATE, &pctl->sctl); |
| 492 | while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) |
| 493 | ; |
| 494 | fallthrough; |
| 495 | case CONFIG: |
| 496 | writel(GO_STATE, &pctl->sctl); |
| 497 | while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG) |
| 498 | ; |
| 499 | break; |
| 500 | case ACCESS: |
| 501 | return; |
| 502 | default: |
| 503 | break; |
| 504 | } |
| 505 | } |
| 506 | } |
| 507 | |
| 508 | static void rk3066_dmc_dram_cfg_rbc(const struct rk3066_dmc_chan_info *chan, u32 chnum, |
| 509 | struct rk3066_dmc_sdram_params *sdram_params) |
| 510 | { |
| 511 | struct rk3288_ddr_publ *publ = chan->publ; |
| 512 | |
| 513 | if (sdram_params->ch[chnum].bk == 3) |
| 514 | clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT, |
| 515 | 1 << PDQ_SHIFT); |
| 516 | else |
| 517 | clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT); |
| 518 | |
| 519 | writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf); |
| 520 | } |
| 521 | |
| 522 | static void rk3066_dmc_dram_all_config(const struct rk3066_dmc_dram_info *dram, |
| 523 | struct rk3066_dmc_sdram_params *sdram_params) |
| 524 | { |
| 525 | unsigned int chan; |
| 526 | u32 sys_reg = 0; |
| 527 | |
| 528 | sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; |
| 529 | sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT; |
| 530 | for (chan = 0; chan < sdram_params->num_channels; chan++) { |
| 531 | const struct rk3288_sdram_channel *info = |
| 532 | &sdram_params->ch[chan]; |
| 533 | |
| 534 | sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan); |
| 535 | sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan); |
| 536 | sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan); |
| 537 | sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan); |
| 538 | sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan); |
| 539 | sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan); |
| 540 | sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan); |
| 541 | sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan); |
| 542 | sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan); |
| 543 | |
| 544 | rk3066_dmc_dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); |
| 545 | } |
| 546 | if (sdram_params->ch[0].rank == 2) |
| 547 | rk3066_dmc_ddr_rank_2_row15en(dram->grf, 0); |
| 548 | else |
| 549 | rk3066_dmc_ddr_rank_2_row15en(dram->grf, 1); |
| 550 | |
| 551 | writel(sys_reg, &dram->pmu->sys_reg[2]); |
| 552 | } |
| 553 | |
| 554 | static int rk3066_dmc_sdram_rank_bw_detect(struct rk3066_dmc_dram_info *dram, int channel, |
| 555 | struct rk3066_dmc_sdram_params *sdram_params) |
| 556 | { |
| 557 | int reg; |
| 558 | int need_trainig = 0; |
| 559 | const struct rk3066_dmc_chan_info *chan = &dram->chan[channel]; |
| 560 | struct rk3288_ddr_publ *publ = chan->publ; |
| 561 | |
| 562 | rk3066_dmc_ddr_rank_2_row15en(dram->grf, 0); |
| 563 | |
| 564 | if (rk3066_dmc_data_training(chan, channel, sdram_params) < 0) { |
| 565 | debug("first data training fail!\n"); |
| 566 | reg = readl(&publ->datx8[0].dxgsr[0]); |
| 567 | /* Check the result for rank 0. */ |
| 568 | if (channel == 0 && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) { |
| 569 | debug("data training fail!\n"); |
| 570 | return -EIO; |
| 571 | } |
| 572 | |
| 573 | /* Check the result for rank 1. */ |
| 574 | if (reg & DQS_GATE_TRAINING_ERROR_RANK1) { |
| 575 | sdram_params->ch[channel].rank = 1; |
| 576 | clrsetbits_le32(&publ->pgcr, 0xF << 18, |
| 577 | sdram_params->ch[channel].rank << 18); |
| 578 | need_trainig = 1; |
| 579 | } |
| 580 | reg = readl(&publ->datx8[2].dxgsr[0]); |
| 581 | if (reg & (1 << 4)) { |
| 582 | sdram_params->ch[channel].bw = 1; |
| 583 | rk3066_dmc_set_bandwidth_ratio(chan, channel, |
| 584 | sdram_params->ch[channel].bw, |
| 585 | dram->grf); |
| 586 | need_trainig = 1; |
| 587 | } |
| 588 | } |
| 589 | /* Assume that the die bit width is equel to the chip bit width. */ |
| 590 | sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw; |
| 591 | |
| 592 | if (need_trainig && |
| 593 | (rk3066_dmc_data_training(chan, channel, sdram_params) < 0)) { |
| 594 | if (sdram_params->base.dramtype == LPDDR3) { |
| 595 | rk3066_dmc_ddr_phy_ctl_reset(dram->cru, channel, 1); |
| 596 | udelay(10); |
| 597 | rk3066_dmc_ddr_phy_ctl_reset(dram->cru, channel, 0); |
| 598 | udelay(10); |
| 599 | } |
| 600 | debug("2nd data training failed!"); |
| 601 | return -EIO; |
| 602 | } |
| 603 | |
| 604 | return 0; |
| 605 | } |
| 606 | |
| 607 | static int rk3066_dmc_sdram_col_row_detect(struct rk3066_dmc_dram_info *dram, int channel, |
| 608 | struct rk3066_dmc_sdram_params *sdram_params) |
| 609 | { |
| 610 | int row, col; |
| 611 | unsigned int addr; |
| 612 | const struct rk3066_dmc_chan_info *chan = &dram->chan[channel]; |
| 613 | struct rk3288_ddr_pctl *pctl = chan->pctl; |
| 614 | struct rk3288_ddr_publ *publ = chan->publ; |
| 615 | int ret = 0; |
| 616 | |
| 617 | /* Detect col. */ |
| 618 | for (col = 11; col >= 9; col--) { |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame^] | 619 | writel(0, CFG_SYS_SDRAM_BASE); |
| 620 | addr = CFG_SYS_SDRAM_BASE + |
Paweł Jarosz | df645ef | 2022-04-16 17:09:41 +0200 | [diff] [blame] | 621 | (1 << (col + sdram_params->ch[channel].bw - 1)); |
| 622 | writel(TEST_PATTERN, addr); |
| 623 | if ((readl(addr) == TEST_PATTERN) && |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame^] | 624 | (readl(CFG_SYS_SDRAM_BASE) == 0)) |
Paweł Jarosz | df645ef | 2022-04-16 17:09:41 +0200 | [diff] [blame] | 625 | break; |
| 626 | } |
| 627 | if (col == 8) { |
| 628 | debug("Col detect error\n"); |
| 629 | ret = -EINVAL; |
| 630 | goto out; |
| 631 | } else { |
| 632 | sdram_params->ch[channel].col = col; |
| 633 | } |
| 634 | |
| 635 | rk3066_dmc_ddr_rank_2_row15en(dram->grf, 1); |
| 636 | rk3066_dmc_move_to_config_state(publ, pctl); |
| 637 | writel(1, &chan->msch->ddrconf); |
| 638 | rk3066_dmc_move_to_access_state(chan); |
| 639 | /* Detect row, max 15, min13 for rk3066 */ |
| 640 | for (row = 16; row >= 13; row--) { |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame^] | 641 | writel(0, CFG_SYS_SDRAM_BASE); |
| 642 | addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); |
Paweł Jarosz | df645ef | 2022-04-16 17:09:41 +0200 | [diff] [blame] | 643 | writel(TEST_PATTERN, addr); |
| 644 | if ((readl(addr) == TEST_PATTERN) && |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame^] | 645 | (readl(CFG_SYS_SDRAM_BASE) == 0)) |
Paweł Jarosz | df645ef | 2022-04-16 17:09:41 +0200 | [diff] [blame] | 646 | break; |
| 647 | } |
| 648 | if (row == 12) { |
| 649 | debug("Row detect error\n"); |
| 650 | ret = -EINVAL; |
| 651 | } else { |
| 652 | sdram_params->ch[channel].cs1_row = row; |
| 653 | sdram_params->ch[channel].row_3_4 = 0; |
| 654 | debug("chn %d col %d, row %d\n", channel, col, row); |
| 655 | sdram_params->ch[channel].cs0_row = row; |
| 656 | } |
| 657 | |
| 658 | out: |
| 659 | return ret; |
| 660 | } |
| 661 | |
| 662 | static int rk3066_dmc_sdram_get_niu_config(struct rk3066_dmc_sdram_params *sdram_params) |
| 663 | { |
| 664 | int i, tmp, size, ret = 0; |
| 665 | |
| 666 | tmp = sdram_params->ch[0].col - 9; |
| 667 | tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1; |
| 668 | tmp |= ((sdram_params->ch[0].cs0_row - 13) << 4); |
| 669 | size = ARRAY_SIZE(rk3066_dmc_ddrconf_table) / sizeof(rk3066_dmc_ddrconf_table[0]); |
| 670 | for (i = 0; i < size; i++) |
| 671 | if (tmp == rk3066_dmc_ddrconf_table[i]) |
| 672 | break; |
| 673 | if (i >= size) { |
| 674 | debug("niu config not found\n"); |
| 675 | ret = -EINVAL; |
| 676 | } else { |
| 677 | debug("niu config %d\n", i); |
| 678 | sdram_params->base.ddrconfig = i; |
| 679 | } |
| 680 | |
| 681 | return ret; |
| 682 | } |
| 683 | |
| 684 | static int rk3066_dmc_sdram_init(struct rk3066_dmc_dram_info *dram, |
| 685 | struct rk3066_dmc_sdram_params *sdram_params) |
| 686 | { |
| 687 | int channel; |
| 688 | int zqcr; |
| 689 | int ret; |
| 690 | |
| 691 | if ((sdram_params->base.dramtype == DDR3 && |
| 692 | sdram_params->base.ddr_freq > 800000000)) { |
| 693 | debug("SDRAM frequency is too high!"); |
| 694 | return -E2BIG; |
| 695 | } |
| 696 | |
| 697 | ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq); |
| 698 | if (ret) { |
| 699 | debug("Could not set DDR clock\n"); |
| 700 | return ret; |
| 701 | } |
| 702 | |
| 703 | for (channel = 0; channel < 1; channel++) { |
| 704 | const struct rk3066_dmc_chan_info *chan = &dram->chan[channel]; |
| 705 | struct rk3288_ddr_pctl *pctl = chan->pctl; |
| 706 | struct rk3288_ddr_publ *publ = chan->publ; |
| 707 | |
| 708 | rk3066_dmc_phy_pctrl_reset(dram->cru, publ, channel); |
| 709 | rk3066_dmc_phy_dll_bypass_set(publ, sdram_params->base.ddr_freq); |
| 710 | |
| 711 | rk3066_dmc_dfi_cfg(pctl, sdram_params->base.dramtype); |
| 712 | |
| 713 | rk3066_dmc_pctl_cfg(channel, pctl, sdram_params, dram->grf); |
| 714 | |
| 715 | rk3066_dmc_phy_cfg(chan, channel, sdram_params); |
| 716 | |
| 717 | rk3066_dmc_phy_init(publ); |
| 718 | |
| 719 | writel(POWER_UP_START, &pctl->powctl); |
| 720 | while (!(readl(&pctl->powstat) & POWER_UP_DONE)) |
| 721 | ; |
| 722 | |
| 723 | rk3066_dmc_memory_init(publ, sdram_params->base.dramtype); |
| 724 | rk3066_dmc_move_to_config_state(publ, pctl); |
| 725 | |
| 726 | /* Use 32bit bus width for detection. */ |
| 727 | sdram_params->ch[channel].bw = 2; |
| 728 | rk3066_dmc_set_bandwidth_ratio(chan, channel, |
| 729 | sdram_params->ch[channel].bw, dram->grf); |
| 730 | /* |
| 731 | * set cs, using n=3 for detect |
| 732 | * CS0, n=1 |
| 733 | * CS1, n=2 |
| 734 | * CS0 & CS1, n = 3 |
| 735 | */ |
| 736 | sdram_params->ch[channel].rank = 2; |
| 737 | clrsetbits_le32(&publ->pgcr, 0xF << 18, |
| 738 | (sdram_params->ch[channel].rank | 1) << 18); |
| 739 | |
| 740 | /* DS=40ohm,ODT=155ohm */ |
| 741 | zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT | |
| 742 | 2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT | |
| 743 | 0x19 << PD_OUTPUT_SHIFT; |
| 744 | writel(zqcr, &publ->zq1cr[0]); |
| 745 | writel(zqcr, &publ->zq0cr[0]); |
| 746 | |
| 747 | /* Detect the rank and bit-width with data-training. */ |
| 748 | writel(1, &chan->msch->ddrconf); |
| 749 | rk3066_dmc_sdram_rank_bw_detect(dram, channel, sdram_params); |
| 750 | |
| 751 | if (sdram_params->base.dramtype == LPDDR3) { |
| 752 | u32 i; |
| 753 | |
| 754 | writel(0, &pctl->mrrcfg0); |
| 755 | |
| 756 | for (i = 0; i < 17; i++) |
| 757 | rk3066_dmc_send_command_op(pctl, 1, MRR_CMD, i, 0); |
| 758 | } |
| 759 | writel(4, &chan->msch->ddrconf); |
| 760 | rk3066_dmc_move_to_access_state(chan); |
| 761 | /* DDR3 and LPDDR3 are always 8 bank, no need to detect. */ |
| 762 | sdram_params->ch[channel].bk = 3; |
| 763 | /* Detect Col and Row number. */ |
| 764 | ret = rk3066_dmc_sdram_col_row_detect(dram, channel, sdram_params); |
| 765 | if (ret) |
| 766 | goto error; |
| 767 | } |
| 768 | /* Find NIU DDR configuration. */ |
| 769 | ret = rk3066_dmc_sdram_get_niu_config(sdram_params); |
| 770 | if (ret) |
| 771 | goto error; |
| 772 | |
| 773 | rk3066_dmc_dram_all_config(dram, sdram_params); |
| 774 | debug("SDRAM init OK!\n"); |
| 775 | |
| 776 | return 0; |
| 777 | error: |
| 778 | debug("SDRAM init failed!\n"); |
| 779 | hang(); |
| 780 | } |
| 781 | |
| 782 | static int rk3066_dmc_setup_sdram(struct udevice *dev) |
| 783 | { |
| 784 | struct rk3066_dmc_dram_info *priv = dev_get_priv(dev); |
| 785 | struct rk3066_dmc_sdram_params *params = dev_get_plat(dev); |
| 786 | |
| 787 | return rk3066_dmc_sdram_init(priv, params); |
| 788 | } |
| 789 | |
| 790 | static int rk3066_dmc_conv_of_plat(struct udevice *dev) |
| 791 | { |
| 792 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
| 793 | struct rk3066_dmc_sdram_params *plat = dev_get_plat(dev); |
| 794 | struct dtd_rockchip_rk3066_dmc *of_plat = &plat->of_plat; |
| 795 | int ret; |
| 796 | |
| 797 | memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing, |
| 798 | sizeof(plat->pctl_timing)); |
| 799 | memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing, |
| 800 | sizeof(plat->phy_timing)); |
| 801 | memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base)); |
| 802 | /* RK3066 supports dual-channel, set default channel num to 2. */ |
| 803 | plat->num_channels = 1; |
| 804 | ret = regmap_init_mem_plat(dev, of_plat->reg, |
| 805 | ARRAY_SIZE(of_plat->reg) / 2, &plat->map); |
| 806 | if (ret) |
| 807 | return ret; |
| 808 | |
| 809 | return 0; |
| 810 | #else |
| 811 | return -EINVAL; |
| 812 | #endif |
| 813 | } |
| 814 | |
| 815 | static int rk3066_dmc_probe(struct udevice *dev) |
| 816 | { |
| 817 | struct rk3066_dmc_dram_info *priv = dev_get_priv(dev); |
| 818 | |
| 819 | priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); |
| 820 | |
| 821 | if (IS_ENABLED(CONFIG_TPL_BUILD)) { |
| 822 | struct rk3066_dmc_sdram_params *plat = dev_get_plat(dev); |
| 823 | struct regmap *map; |
| 824 | struct udevice *dev_clk; |
| 825 | int ret; |
| 826 | |
| 827 | ret = rk3066_dmc_conv_of_plat(dev); |
| 828 | if (ret) |
| 829 | return ret; |
| 830 | |
| 831 | map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC); |
| 832 | if (IS_ERR(map)) |
| 833 | return PTR_ERR(map); |
| 834 | priv->chan[0].msch = regmap_get_range(map, 0); |
| 835 | priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); |
| 836 | |
| 837 | priv->chan[0].pctl = regmap_get_range(plat->map, 0); |
| 838 | priv->chan[0].publ = regmap_get_range(plat->map, 1); |
| 839 | |
| 840 | ret = rockchip_get_clk(&dev_clk); |
| 841 | if (ret) |
| 842 | return ret; |
| 843 | |
| 844 | priv->ddr_clk.id = CLK_DDR; |
| 845 | ret = clk_request(dev_clk, &priv->ddr_clk); |
| 846 | if (ret) |
| 847 | return ret; |
| 848 | |
| 849 | priv->cru = rockchip_get_cru(); |
| 850 | if (IS_ERR(priv->cru)) |
| 851 | return PTR_ERR(priv->cru); |
| 852 | |
| 853 | ret = rk3066_dmc_setup_sdram(dev); |
| 854 | if (ret) |
| 855 | return ret; |
| 856 | } else { |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame^] | 857 | priv->info.base = CFG_SYS_SDRAM_BASE; |
Paweł Jarosz | df645ef | 2022-04-16 17:09:41 +0200 | [diff] [blame] | 858 | priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->pmu->sys_reg[2]); |
| 859 | } |
| 860 | |
| 861 | return 0; |
| 862 | } |
| 863 | |
| 864 | static int rk3066_dmc_get_info(struct udevice *dev, struct ram_info *info) |
| 865 | { |
| 866 | struct rk3066_dmc_dram_info *priv = dev_get_priv(dev); |
| 867 | |
| 868 | *info = priv->info; |
| 869 | |
| 870 | return 0; |
| 871 | } |
| 872 | |
| 873 | static struct ram_ops rk3066_dmc_ops = { |
| 874 | .get_info = rk3066_dmc_get_info, |
| 875 | }; |
| 876 | |
| 877 | static const struct udevice_id rk3066_dmc_ids[] = { |
| 878 | { .compatible = "rockchip,rk3066-dmc" }, |
| 879 | { } |
| 880 | }; |
| 881 | |
| 882 | U_BOOT_DRIVER(rockchip_rk3066_dmc) = { |
| 883 | .name = "rockchip_rk3066_dmc", |
| 884 | .id = UCLASS_RAM, |
| 885 | .ops = &rk3066_dmc_ops, |
| 886 | .probe = rk3066_dmc_probe, |
| 887 | .of_match = rk3066_dmc_ids, |
| 888 | .priv_auto = sizeof(struct rk3066_dmc_dram_info), |
| 889 | #if IS_ENABLED(CONFIG_TPL_BUILD) |
| 890 | .plat_auto = sizeof(struct rk3066_dmc_sdram_params), |
| 891 | #endif |
| 892 | }; |