weichangzheng | 74b4519 | 2022-03-02 15:09:05 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2021 |
| 4 | * lixinde <lixinde@phytium.com.cn> |
| 5 | * weichangzheng <weichangzheng@phytium.com.cn> |
| 6 | */ |
| 7 | |
| 8 | #include <stdio.h> |
| 9 | #include <command.h> |
| 10 | #include <init.h> |
| 11 | #include <asm/armv8/mmu.h> |
| 12 | #include <asm/io.h> |
| 13 | #include <linux/arm-smccc.h> |
| 14 | #include <scsi.h> |
| 15 | #include <init.h> |
| 16 | #include <asm/u-boot.h> |
| 17 | #include "cpu.h" |
| 18 | |
| 19 | DECLARE_GLOBAL_DATA_PTR; |
| 20 | |
| 21 | int dram_init(void) |
| 22 | { |
| 23 | debug("Phytium ddr init\n"); |
| 24 | ddr_init(); |
| 25 | |
| 26 | gd->mem_clk = 0; |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame^] | 27 | gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, 0x7b000000); |
weichangzheng | 74b4519 | 2022-03-02 15:09:05 +0800 | [diff] [blame] | 28 | |
| 29 | sec_init(); |
| 30 | debug("PBF relocate done\n"); |
| 31 | |
| 32 | return 0; |
| 33 | } |
| 34 | |
| 35 | int board_init(void) |
| 36 | { |
| 37 | return 0; |
| 38 | } |
| 39 | |
| 40 | void reset_cpu(void) |
| 41 | { |
| 42 | struct arm_smccc_res res; |
| 43 | |
| 44 | debug("run in reset cpu\n"); |
| 45 | arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res); |
| 46 | if (res.a0 != 0) |
| 47 | panic("reset cpu error, %lx\n", res.a0); |
| 48 | } |
| 49 | |
| 50 | int mach_cpu_init(void) |
| 51 | { |
| 52 | check_reset(); |
| 53 | return 0; |
| 54 | } |
| 55 | |
| 56 | int board_early_init_f(void) |
| 57 | { |
| 58 | pcie_init(); |
| 59 | return 0; |
| 60 | } |
| 61 | |
| 62 | static struct mm_region pomelo_mem_map[] = { |
| 63 | { |
| 64 | .virt = 0x0UL, |
| 65 | .phys = 0x0UL, |
| 66 | .size = 0x80000000UL, |
| 67 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 68 | PTE_BLOCK_NON_SHARE | |
| 69 | PTE_BLOCK_PXN | |
| 70 | PTE_BLOCK_UXN |
| 71 | }, |
| 72 | { |
| 73 | .virt = 0x80000000UL, |
| 74 | .phys = 0x80000000UL, |
| 75 | .size = 0x7b000000UL, |
| 76 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 77 | PTE_BLOCK_NS | |
| 78 | PTE_BLOCK_INNER_SHARE |
| 79 | }, |
| 80 | { |
| 81 | 0, |
| 82 | } |
| 83 | }; |
| 84 | |
| 85 | struct mm_region *mem_map = pomelo_mem_map; |
| 86 | |
| 87 | int __asm_flush_l3_dcache(void) |
| 88 | { |
| 89 | int i, pstate; |
| 90 | |
| 91 | for (i = 0; i < HNF_COUNT; i++) |
| 92 | writeq(HNF_PSTATE_SFONLY, HNF_PSTATE_REQ + i * HNF_STRIDE); |
| 93 | for (i = 0; i < HNF_COUNT; i++) { |
| 94 | do { |
| 95 | pstate = readq(HNF_PSTATE_STAT + i * HNF_STRIDE); |
| 96 | } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); |
| 97 | } |
| 98 | |
| 99 | for (i = 0; i < HNF_COUNT; i++) |
| 100 | writeq(HNF_PSTATE_FULL, HNF_PSTATE_REQ + i * HNF_STRIDE); |
| 101 | |
| 102 | return 0; |
| 103 | } |
| 104 | |
| 105 | int last_stage_init(void) |
| 106 | { |
| 107 | int ret; |
| 108 | |
| 109 | /* pci e */ |
| 110 | pci_init(); |
| 111 | /* scsi scan */ |
| 112 | ret = scsi_scan(true); |
| 113 | if (ret) { |
| 114 | printf("scsi scan failed\n"); |
| 115 | return CMD_RET_FAILURE; |
| 116 | } |
| 117 | return ret; |
| 118 | } |