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git01.mediatek.com / filogic / uboot / bb28ec52a57555edf6c1a736bed8c766070bb5e6 / . / board / olimex / mx23_olinuxino / spl_boot.c
blob: eb85ce9643d8f753170930e07aa8af170f02903f [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Marek Vasut189e35b2013-01-12 07:11:11 +0000[diff] [blame]2/*
3 * Olimex MX23 Olinuxino Boot setup
4 *
5 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
Marek Vasut189e35b2013-01-12 07:11:11 +0000[diff] [blame]6 */
7
Marek Vasut189e35b2013-01-12 07:11:11 +0000[diff] [blame]8#include <config.h>
9#include <asm/io.h>
10#include <asm/arch/iomux-mx23.h>
11#include <asm/arch/imx-regs.h>
12#include <asm/arch/sys_proto.h>
13
Fabio Estevamf30d14b2013-05-03 04:37:09 +0000[diff] [blame]14#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
Fabio Estevam1716d932013-05-05 15:52:56 +0000[diff] [blame]15#define MUX_CONFIG_SSP (MXS_PAD_8MA | MXS_PAD_PULLUP)
Marek Vasut189e35b2013-01-12 07:11:11 +0000[diff] [blame]16
17const iomux_cfg_t iomux_setup[] = {
18 /* DUART */
19 MX23_PAD_PWM0__DUART_RX,
20 MX23_PAD_PWM1__DUART_TX,
21
22 /* EMI */
23 MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI,
24 MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI,
25 MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI,
26 MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI,
27 MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI,
28 MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI,
29 MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI,
30 MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI,
31 MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI,
32 MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI,
33 MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI,
34 MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI,
35 MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI,
36 MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI,
37 MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI,
38 MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI,
39 MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
40 MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
41 MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
42 MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
43 MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
44 MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI,
45
46 MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI,
47 MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI,
48 MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI,
49 MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI,
50 MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI,
51 MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI,
52 MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI,
53 MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI,
54 MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI,
55 MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI,
56 MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI,
57 MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI,
58 MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI,
59 MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
60 MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
61
62 MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
63 MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
64 MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
65 MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
66 MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
67 MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
Marek Vasut73f2b032013-01-22 15:01:05 +0000[diff] [blame]68
Otavio Salvadorfcc76892013-02-23 02:43:09 +0000[diff] [blame]69 /* Green LED */
70 MX23_PAD_SSP1_DETECT__GPIO_2_1 |
71 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL),
72
Marek Vasut73f2b032013-01-22 15:01:05 +0000[diff] [blame]73 /* MMC 0 */
74 MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP,
75 MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP,
76 MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP,
77 MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP,
78 MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP,
79 MX23_PAD_SSP1_SCK__SSP1_SCK | MUX_CONFIG_SSP,
Otavio Salvador801fa152013-03-02 05:17:29 +0000[diff] [blame]80
81 /* Ethernet */
82 MX23_PAD_GPMI_ALE__GPIO_0_17 |
83 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
Marek Vasut189e35b2013-01-12 07:11:11 +0000[diff] [blame]84};
85
Marek Vasut0dc62ba2013-08-31 15:53:44 +0200[diff] [blame]86void board_init_ll(const uint32_t arg, const uint32_t *resptr)
Marek Vasut189e35b2013-01-12 07:11:11 +0000[diff] [blame]87{
Marek Vasut0dc62ba2013-08-31 15:53:44 +0200[diff] [blame]88 mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
Marek Vasut189e35b2013-01-12 07:11:11 +0000[diff] [blame]89}
Jan Luebbe1f4bcbc2014-12-14 16:34:49 +0100[diff] [blame]90
91/* Fine-tune the DRAM configuration. */
92void mxs_adjust_memory_params(uint32_t *dram_vals)
93{
94 /* Enable Auto Precharge. */
95 dram_vals[3] |= 1 << 8;
96 /* Enable Fast Writes. */
97 dram_vals[5] |= 1 << 8;
98 /* tEMRS = 3*tCK */
99 dram_vals[10] &= ~(0x3 << 8);
100 dram_vals[10] |= (0x3 << 8);
101 /* CASLAT = 3*tCK */
102 dram_vals[11] &= ~(0x3 << 0);
103 dram_vals[11] |= (0x3 << 0);
104 /* tCKE = 1*tCK */
105 dram_vals[12] &= ~(0x7 << 0);
106 dram_vals[12] |= (0x1 << 0);
107 /* CASLAT_LIN_GATE = 3*tCK , CASLAT_LIN = 3*tCK, tWTR=2*tCK */
108 dram_vals[13] &= ~((0xf << 16) | (0xf << 24) | (0xf << 0));
109 dram_vals[13] |= (0x6 << 16) | (0x6 << 24) | (0x2 << 0);
110 /* tDAL = 6*tCK */
111 dram_vals[15] &= ~(0xf << 16);
112 dram_vals[15] |= (0x6 << 16);
113 /* tREF = 1040*tCK */
114 dram_vals[26] &= ~0xffff;
115 dram_vals[26] |= 0x0410;
116 /* tRAS_MAX = 9334*tCK */
117 dram_vals[32] &= ~0xffff;
118 dram_vals[32] |= 0x2475;
119}