Marek Vasut | f670cd7 | 2022-05-21 16:56:26 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright 2022 Marek Vasut <marex@denx.de> |
| 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <hang.h> |
| 8 | #include <image.h> |
| 9 | #include <init.h> |
| 10 | #include <spl.h> |
| 11 | #include <asm/io.h> |
| 12 | #include <asm-generic/gpio.h> |
| 13 | #include <asm/arch/clock.h> |
| 14 | #include <asm/arch/imx8mp_pins.h> |
| 15 | #include <asm/arch/sys_proto.h> |
| 16 | #include <asm/mach-imx/boot_mode.h> |
| 17 | #include <asm/arch/ddr.h> |
Shiji Yang | bb11234 | 2023-08-03 09:47:16 +0800 | [diff] [blame^] | 18 | #include <asm/sections.h> |
Marek Vasut | f670cd7 | 2022-05-21 16:56:26 +0200 | [diff] [blame] | 19 | |
| 20 | #include <dm/uclass.h> |
| 21 | #include <dm/device.h> |
| 22 | #include <dm/uclass-internal.h> |
| 23 | #include <dm/device-internal.h> |
| 24 | |
| 25 | #include <power/pmic.h> |
| 26 | #include <power/pca9450.h> |
| 27 | |
| 28 | #include "lpddr4_timing.h" |
| 29 | |
| 30 | DECLARE_GLOBAL_DATA_PTR; |
| 31 | |
| 32 | #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) |
| 33 | #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) |
| 34 | |
| 35 | static const iomux_v3_cfg_t uart_pads[] = { |
| 36 | MX8MP_PAD_SAI2_RXFS__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 37 | MX8MP_PAD_SAI2_RXC__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 38 | }; |
| 39 | |
| 40 | static const iomux_v3_cfg_t wdog_pads[] = { |
| 41 | MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), |
| 42 | }; |
| 43 | |
| 44 | static void dh_imx8mp_early_init_f(void) |
| 45 | { |
| 46 | struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; |
| 47 | |
| 48 | imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); |
| 49 | |
| 50 | set_wdog_reset(wdog); |
| 51 | |
| 52 | imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); |
| 53 | } |
| 54 | |
| 55 | static int dh_imx8mp_board_power_init(void) |
| 56 | { |
| 57 | struct udevice *dev; |
| 58 | int ret; |
| 59 | |
| 60 | ret = pmic_get("pmic@25", &dev); |
| 61 | if (ret == -ENODEV) { |
| 62 | puts("Failed to get PMIC\n"); |
| 63 | return 0; |
| 64 | } |
| 65 | if (ret != 0) |
| 66 | return ret; |
| 67 | |
| 68 | /* BUCKxOUT_DVS0/1 control BUCK123 output. */ |
| 69 | pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); |
| 70 | |
| 71 | /* Increase VDD_SOC to typical value 0.95V before first DRAM access. */ |
| 72 | if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV)) |
| 73 | /* Set DVS0 to 0.85V for special case. */ |
| 74 | pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); |
| 75 | else |
| 76 | pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1c); |
| 77 | |
| 78 | /* Set DVS1 to 0.85v for suspend. */ |
| 79 | pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); |
| 80 | |
| 81 | /* |
| 82 | * Enable DVS control through PMIC_STBY_REQ and |
| 83 | * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H). |
| 84 | */ |
| 85 | pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); |
| 86 | |
| 87 | /* Kernel uses OD/OD frequency for SoC. */ |
| 88 | |
| 89 | /* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95V */ |
| 90 | pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c); |
| 91 | |
Marek Vasut | f670cd7 | 2022-05-21 16:56:26 +0200 | [diff] [blame] | 92 | /* Set LDO4 and CONFIG2 to enable the I2C level translator. */ |
| 93 | pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59); |
| 94 | pmic_reg_write(dev, PCA9450_CONFIG2, 0x1); |
| 95 | |
| 96 | return 0; |
| 97 | } |
| 98 | |
| 99 | static struct dram_timing_info *dram_timing_info[8] = { |
| 100 | NULL, /* 512 MiB */ |
| 101 | NULL, /* 1024 MiB */ |
| 102 | NULL, /* 1536 MiB */ |
Marek Vasut | 9fa78d6 | 2023-02-11 22:49:01 +0100 | [diff] [blame] | 103 | &dh_imx8mp_dhcom_dram_timing_16g_x32, /* 2048 MiB */ |
Marek Vasut | f670cd7 | 2022-05-21 16:56:26 +0200 | [diff] [blame] | 104 | NULL, /* 3072 MiB */ |
| 105 | &dh_imx8mp_dhcom_dram_timing_32g_x32, /* 4096 MiB */ |
| 106 | NULL, /* 6144 MiB */ |
| 107 | NULL, /* 8192 MiB */ |
| 108 | }; |
| 109 | |
| 110 | static void spl_dram_init(void) |
| 111 | { |
| 112 | const u16 size[] = { 512, 1024, 1536, 2048, 3072, 4096, 6144, 8192 }; |
| 113 | u8 memcfg = dh_get_memcfg(); |
| 114 | int i; |
| 115 | |
| 116 | printf("DDR: %d MiB [0x%x]\n", size[memcfg], memcfg); |
| 117 | |
| 118 | if (!dram_timing_info[memcfg]) { |
| 119 | printf("Unsupported DRAM strapping, trying lowest supported. MEMCFG=0x%x\n", |
| 120 | memcfg); |
| 121 | for (i = 0; i < ARRAY_SIZE(dram_timing_info); i++) |
| 122 | if (dram_timing_info[i]) /* Configuration found */ |
| 123 | break; |
| 124 | } |
| 125 | |
| 126 | ddr_init(dram_timing_info[memcfg]); |
| 127 | } |
| 128 | |
| 129 | void spl_board_init(void) |
| 130 | { |
| 131 | /* |
| 132 | * Set GIC clock to 500 MHz for OD VDD_SOC. Kernel driver does not |
| 133 | * allow to change it. Should set the clock after PMIC setting done. |
| 134 | * Default is 400 MHz (system_pll1_800m with div = 2) set by ROM for |
| 135 | * ND VDD_SOC. |
| 136 | */ |
| 137 | clock_enable(CCGR_GIC, 0); |
| 138 | clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5)); |
| 139 | clock_enable(CCGR_GIC, 1); |
| 140 | } |
| 141 | |
| 142 | int spl_board_boot_device(enum boot_device boot_dev_spl) |
| 143 | { |
| 144 | return BOOT_DEVICE_BOOTROM; |
| 145 | } |
| 146 | |
| 147 | void board_init_f(ulong dummy) |
| 148 | { |
| 149 | struct udevice *dev; |
| 150 | int ret; |
| 151 | |
| 152 | arch_cpu_init(); |
| 153 | |
| 154 | init_uart_clk(0); |
| 155 | |
| 156 | dh_imx8mp_early_init_f(); |
| 157 | |
| 158 | preloader_console_init(); |
| 159 | |
| 160 | /* Clear the BSS. */ |
| 161 | memset(__bss_start, 0, __bss_end - __bss_start); |
| 162 | |
| 163 | ret = spl_early_init(); |
| 164 | if (ret) { |
| 165 | debug("spl_early_init() failed: %d\n", ret); |
| 166 | hang(); |
| 167 | } |
| 168 | |
| 169 | ret = uclass_get_device_by_name(UCLASS_CLK, |
| 170 | "clock-controller@30380000", |
| 171 | &dev); |
| 172 | if (ret < 0) { |
| 173 | printf("Failed to find clock node. Check device tree\n"); |
| 174 | hang(); |
| 175 | } |
| 176 | |
| 177 | enable_tzc380(); |
| 178 | |
| 179 | dh_imx8mp_board_power_init(); |
| 180 | |
| 181 | /* DDR initialization */ |
| 182 | spl_dram_init(); |
| 183 | |
| 184 | board_init_r(NULL, 0); |
| 185 | } |