| developer | 2fddd72 | 2022-05-20 11:22:21 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (C) 2022 MediaTek Inc. All rights reserved. |
| 4 | * |
| 5 | * Author: Weijie Gao <weijie.gao@mediatek.com> |
| 6 | */ |
| 7 | |
| 8 | #ifndef _MT7621_DRAM_H_ |
| 9 | #define _MT7621_DRAM_H_ |
| 10 | |
| 11 | #define STAGE_LOAD_ADDR 0xBE108800 |
| 12 | |
| 13 | #ifndef __ASSEMBLY__ |
| 14 | #include <linux/types.h> |
| 15 | |
| 16 | #define DDR_PARAM_SIZE 24 |
| 17 | |
| 18 | struct stage_header { |
| 19 | u32 jump_insn[2]; |
| 20 | u32 ep; |
| 21 | u32 stage_size; |
| 22 | u32 has_stage2; |
| 23 | u32 next_ep; |
| 24 | u32 next_size; |
| 25 | u32 next_offset; |
| 26 | u32 cpu_pll_cfg; |
| 27 | u32 ddr_pll_cfg; |
| 28 | u32 reserved2[6]; |
| 29 | char build_tag[32]; |
| 30 | u32 ddr3_act[DDR_PARAM_SIZE]; |
| 31 | u32 padding1[2]; |
| 32 | u32 ddr2_act[DDR_PARAM_SIZE]; |
| 33 | u32 padding2[2]; |
| 34 | u32 baudrate; |
| 35 | u32 padding3; |
| 36 | }; |
| 37 | #endif |
| 38 | |
| 39 | #endif /* _MT7621_DRAM_H_ */ |