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git01.mediatek.com / filogic / uboot / bace46758697727f6be0af5110dcbdaf432487cc / . / arch / arm / dts / k3-am62-wakeup.dtsi
blob: 23ce1bfda8d6abbb75472d3b8a321f6e9eb3d8c3 [file] [log] [blame]
Roger Quadrosbace4672024-05-13 15:13:54 +0300[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0-only OR MIT
Suman Anna7e0cfeb2022-05-25 13:38:46 +0530[diff] [blame]2/*
3 * Device Tree Source for AM625 SoC Family Wakeup Domain peripherals
4 *
Roger Quadrosbace4672024-05-13 15:13:54 +0300[diff] [blame^]5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
Suman Anna7e0cfeb2022-05-25 13:38:46 +0530[diff] [blame]6 */
7
Roger Quadrosbace4672024-05-13 15:13:54 +0300[diff] [blame^]8#include <dt-bindings/bus/ti-sysc.h>
9
Suman Anna7e0cfeb2022-05-25 13:38:46 +0530[diff] [blame]10&cbass_wakeup {
11 wkup_conf: syscon@43000000 {
Nishanth Menonc72e8e72023-11-14 21:28:54 -0600[diff] [blame]12 bootph-all;
Suman Anna7e0cfeb2022-05-25 13:38:46 +0530[diff] [blame]13 compatible = "syscon", "simple-mfd";
14 reg = <0x00 0x43000000 0x00 0x20000>;
15 #address-cells = <1>;
16 #size-cells = <1>;
17 ranges = <0x0 0x00 0x43000000 0x20000>;
18
19 chipid: chipid@14 {
Nishanth Menonc72e8e72023-11-14 21:28:54 -0600[diff] [blame]20 bootph-all;
Suman Anna7e0cfeb2022-05-25 13:38:46 +0530[diff] [blame]21 compatible = "ti,am654-chipid";
22 reg = <0x14 0x4>;
23 };
24 };
25
Roger Quadrosbace4672024-05-13 15:13:54 +0300[diff] [blame^]26 target-module@2b300050 {
27 compatible = "ti,sysc-omap2", "ti,sysc";
28 reg = <0x00 0x2b300050 0x00 0x4>,
29 <0x00 0x2b300054 0x00 0x4>,
30 <0x00 0x2b300058 0x00 0x4>;
31 reg-names = "rev", "sysc", "syss";
32 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
33 SYSC_OMAP2_SOFTRESET |
34 SYSC_OMAP2_AUTOIDLE)>;
35 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
36 <SYSC_IDLE_NO>,
37 <SYSC_IDLE_SMART>,
38 <SYSC_IDLE_SMART_WKUP>;
39 ti,syss-mask = <1>;
40 ti,no-reset-on-init;
Suman Anna7e0cfeb2022-05-25 13:38:46 +0530[diff] [blame]41 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
42 clocks = <&k3_clks 114 0>;
Roger Quadrosbace4672024-05-13 15:13:54 +0300[diff] [blame^]43 clock-names = "fck";
44 #address-cells = <1>;
45 #size-cells = <1>;
46 ranges = <0x0 0x00 0x2b300000 0x100000>;
47
48 wkup_uart0: serial@0 {
49 compatible = "ti,am64-uart", "ti,am654-uart";
50 reg = <0x0 0x100>;
51 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
52 status = "disabled";
53 };
Suman Anna7e0cfeb2022-05-25 13:38:46 +0530[diff] [blame]54 };
55
56 wkup_i2c0: i2c@2b200000 {
57 compatible = "ti,am64-i2c", "ti,omap4-i2c";
Nishanth Menone17596d2023-07-27 04:03:31 -0500[diff] [blame]58 reg = <0x00 0x2b200000 0x00 0x100>;
Suman Anna7e0cfeb2022-05-25 13:38:46 +0530[diff] [blame]59 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
60 #address-cells = <1>;
61 #size-cells = <0>;
62 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
63 clocks = <&k3_clks 107 4>;
64 clock-names = "fck";
Nishanth Menone17596d2023-07-27 04:03:31 -0500[diff] [blame]65 status = "disabled";
66 };
67
68 wkup_rtc0: rtc@2b1f0000 {
69 compatible = "ti,am62-rtc";
70 reg = <0x00 0x2b1f0000 0x00 0x100>;
71 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
72 clocks = <&k3_clks 117 6> , <&k3_clks 117 0>;
73 clock-names = "vbus", "osc32k";
74 power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>;
75 wakeup-source;
76 };
77
78 wkup_rti0: watchdog@2b000000 {
79 compatible = "ti,j7-rti-wdt";
80 reg = <0x00 0x2b000000 0x00 0x100>;
81 clocks = <&k3_clks 132 0>;
82 power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>;
83 assigned-clocks = <&k3_clks 132 0>;
84 assigned-clock-parents = <&k3_clks 132 2>;
85 /* Used by DM firmware */
86 status = "reserved";
87 };
88
89 wkup_vtm0: temperature-sensor@b00000 {
90 compatible = "ti,j7200-vtm";
91 reg = <0x00 0xb00000 0x00 0x400>,
92 <0x00 0xb01000 0x00 0x400>;
93 power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
94 #thermal-sensor-cells = <1>;
Suman Anna7e0cfeb2022-05-25 13:38:46 +0530[diff] [blame]95 };
96};