| Neil Armstrong | 85c4a52 | 2022-07-06 11:36:49 +0200 | [diff] [blame] | 1 | .. SPDX-License-Identifier: GPL-2.0+ |
| 2 | |
| 3 | Amlogic SoC Boot Flow |
| 4 | ===================== |
| 5 | |
| 6 | The Amlogic SoCs have a pre-defined boot sequence in the SoC ROM code. Here are |
| 7 | the possible boot sources of different SoC families supported by U-Boot: |
| 8 | |
| 9 | GX* & AXG family |
| 10 | ---------------- |
| 11 | |
| 12 | +----------+--------------------+-------+-------+---------------+---------------+ |
| 13 | | | 1 | 2 | 3 | 4 | 5 | |
| 14 | +==========+====================+=======+=======+===============+===============+ |
| 15 | | S905 | POC=0: SPI NOR | eMMC | NAND | SD Card | USB Device | |
| 16 | | S905X | | | | | | |
| 17 | | S905L | | | | | | |
| 18 | | S905W | | | | | | |
| 19 | | S912 | | | | | | |
| 20 | +----------+--------------------+-------+-------+---------------+---------------+ |
| 21 | | S805X | POC=0: SPI NOR | eMMC | NAND | USB Device | - | |
| 22 | | A113D | | | | | | |
| 23 | | A113X | | | | | | |
| 24 | +----------+--------------------+-------+-------+---------------+---------------+ |
| 25 | |
| 26 | POC pin: `NAND_CLE` |
| 27 | |
| 28 | Some boards provide a button to force USB BOOT which disables the eMMC clock signal |
| 29 | to bypass the eMMC stage. Others have removable eMMC modules; removing the eMMC and |
| 30 | SDCard will allow boot from USB. |
| 31 | |
| 32 | An exception is the lafrite board (aml-s805x-xx) which has no SDCard slot and boots |
| 33 | from SPI. The only ways to boot the lafrite board from USB are: |
| 34 | |
| 35 | - Erase the first sectors of SPI NOR flash |
| 36 | - Insert an HDMI boot plug forcing boot over USB |
| 37 | |
| 38 | The VIM1 and initial VIM2 boards provide a test point on the eMMC signals to block |
| 39 | the storage from answering and continue to the next boot step. |
| 40 | |
| 41 | The USB Device boot uses the first USB interface. On some boards this port is only |
| 42 | available on an USB-A type connector and needs an special Type-A to Type-A cable to |
| 43 | communicate with the BootROM. |
| 44 | |
| 45 | G12* & SM1 family |
| 46 | ----------------- |
| 47 | |
| 48 | +-------+-------+-------+---------------+---------------+---------------+---------------+ |
| 49 | | POC0 | POC1 | POC2 | 1 | 2 | 3 | 4 | |
| 50 | +=======+=======+=======+===============+===============+===============+===============+ |
| 51 | | 0 | 0 | 0 | USB Device | SPI NOR | NAND/eMMC | SDCard | |
| 52 | +-------+-------+-------+---------------+---------------+---------------+---------------+ |
| 53 | | 0 | 0 | 1 | USB Device | NAND/eMMC | SDCard | - | |
| 54 | +-------+-------+-------+---------------+---------------+---------------+---------------+ |
| 55 | | 0 | 1 | 0 | SPI NOR | NAND/eMMC | SDCard | USB Device | |
| 56 | +-------+-------+-------+---------------+---------------+---------------+---------------+ |
| 57 | | 0 | 1 | 1 | SPI NAND | NAND/eMMC | USB Device | - | |
| 58 | +-------+-------+-------+---------------+---------------+---------------+---------------+ |
| 59 | | 1 | 0 | 0 | USB Device | SPI NOR | NAND/eMMC | SDCard | |
| 60 | +-------+-------+-------+---------------+---------------+---------------+---------------+ |
| 61 | | 1 | 0 | 1 | USB Device | NAND/eMMC | SDCard | - | |
| 62 | +-------+-------+-------+---------------+---------------+---------------+---------------+ |
| 63 | | 1 | 1 | 0 | SPI NOR | NAND/eMMC | SDCard | USB Device | |
| 64 | +-------+-------+-------+---------------+---------------+---------------+---------------+ |
| 65 | | 1 | 1 | 1 | NAND/eMMC | SDCard | USB Device | - | |
| 66 | +-------+-------+-------+---------------+---------------+---------------+---------------+ |
| 67 | |
| 68 | The last option (1/1/1) is the normal default seen on production devices. |
| 69 | |
| 70 | * POC0 pin: `BOOT_4` (0 and all other 1 means SPI NAND boot first) |
| 71 | * POC1 pin: `BOOT_5` (0 and all other 1 means USB Device boot first |
| 72 | * POC2 pin: `BOOT_6` (0 and all other 1 means SPI NOR boot first) |
| 73 | |
| 74 | Most boards provide a button to force USB BOOT which lowers `BOOT_5` to 0. Some boards |
| 75 | provide a test point on the eMMC or SPI NOR clock signals to block the storage from |
| 76 | answering and continue to the next boot step. |
| 77 | |
| 78 | The Khadas VIM3/3L boards embed a microcontroller which sets POC signals according |
| 79 | to its configuration or a specific key press sequence to either boot from SPI NOR |
| 80 | or eMMC then SDCard, or boot as an USB Device. |
| 81 | |
| 82 | The Odroid N2/N2+ has a hardware switch to select between SPI NOR or eMMC boot. |
| 83 | |
| 84 | Boot Modes |
| 85 | ---------- |
| 86 | |
| 87 | * SDCard |
| 88 | |
| 89 | The BootROM fetches the first SDCard sectors in one sequence, then checks the content |
| 90 | of the data. The BootROM expects to find the FIP binary in sector 1, 512 bytes offset |
| 91 | from the start. |
| 92 | |
| 93 | * eMMC |
| 94 | |
| 95 | The BootROM fetches the first sectors in one sequence, first on the main partition, |
| 96 | and then on the Boot0 followed by Boot1 HW partitions. After each read, the BootROM |
| 97 | checks the data and looks to the next partition if it fails. The BootROM expects to |
| 98 | find the FIP binary in sector 1, 512 bytes offset from the start. |
| 99 | |
| 100 | * SPI NOR |
| 101 | |
| 102 | The BootROM fetches the first SPI NOR sectors in one sequence, then checks the content |
| 103 | of the data. The BootROM expects to find the FIP binary in sector 1, 512 bytes offset |
| 104 | from the start. |
| 105 | |
| 106 | * NAND & SPI NAND |
| 107 | |
| 108 | These modes are rarely used in open platforms and no details are available. |
| 109 | |
| 110 | * USB Device |
| 111 | |
| 112 | The BootROM sets the USB Gadget interface to serve a custom USB protocol with the |
| 113 | USB ID 1b8e:c003. The Amlogic `update` utility is designed to use this protocol. It |
| 114 | is also implemented in the Amlogic Vendor U-Boot. |
| 115 | |
| 116 | The open-source `pyamlboot` utility https://github.com/superna9999/pyamlboot also |
| 117 | implements this protocol and can load U-Boot in memory in order to start the SoC |
| 118 | without any attached storage or to recover from a failed/incorrect image flash. |
| 119 | |
| 120 | HDMI Recovery |
| 121 | ------------- |
| 122 | |
| 123 | The BootROM also briefly reads 8 bytes at address I2C 0x52 offset 0xf8 (248) on the |
| 124 | HDMI DDC bus. If the content is `boot@USB` it will force USB boot mode. If the content |
| 125 | is `boot@SDC` it will force SDCard boot mode. |
| 126 | |
| 127 | If USB Device doesn't enumerate or SD Card boot step doesn't work, the BootROM will |
| 128 | continue with the normal boot sequence. |
| 129 | |
| 130 | Special boot dongles can be built by connecting a 256bytes EEPROM set to answer on |
| 131 | address 0x52, and program `boot@USB` or `boot@SDC` at offset 0xf8 (248). |
| 132 | |
| 133 | Note: If the SoC is booted with USB Device forced at first step, it will keep the boot |
| 134 | order on warm reboot. Only cold reboot (power removed) will reset the boot order. |