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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Jason Cooper8d038fa2011-10-03 13:49:53 +05302/*
Tony Dinh179dd642022-01-30 15:02:30 -08003 * Copyright (C) 2021-2022 Tony Dinh <mibodhi@gmail.com>
4 * Copyright (C) 2011 Jason Cooper <u-boot@lakedaemon.net>
Jason Cooper8d038fa2011-10-03 13:49:53 +05305 *
6 * Based on work by:
7 * Marvell Semiconductor <www.marvell.com>
8 * Written-by: Siddarth Gore <gores@marvell.com>
Jason Cooper8d038fa2011-10-03 13:49:53 +05309 */
10
11#include <common.h>
Simon Glass97589732020-05-10 11:40:02 -060012#include <init.h>
Tony Dinh179dd642022-01-30 15:02:30 -080013#include <netdev.h>
Anatolij Gustschincc942142011-10-29 11:19:47 +000014#include <asm/arch/cpu.h>
Stefan Roesec2437842014-10-22 12:13:06 +020015#include <asm/arch/soc.h>
Jason Cooper8d038fa2011-10-03 13:49:53 +053016#include <asm/arch/mpp.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060017#include <asm/global_data.h>
Jason Cooper8d038fa2011-10-03 13:49:53 +053018
19DECLARE_GLOBAL_DATA_PTR;
20
Tony Dinh179dd642022-01-30 15:02:30 -080021#define DREAMPLUG_OE_LOW (~(0))
22#define DREAMPLUG_OE_HIGH (~(0))
23#define DREAMPLUG_OE_VAL_LOW 0
24#define DREAMPLUG_OE_VAL_HIGH (0xf << 16) /* 4 LED Pins high */
25
Jason Cooper8d038fa2011-10-03 13:49:53 +053026int board_early_init_f(void)
27{
28 /*
29 * default gpio configuration
30 * There are maximum 64 gpios controlled through 2 sets of registers
31 * the below configuration configures mainly initial LED status
32 */
Stefan Roesec50ab392014-10-22 12:13:11 +020033 mvebu_config_gpio(DREAMPLUG_OE_VAL_LOW,
34 DREAMPLUG_OE_VAL_HIGH,
35 DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
Jason Cooper8d038fa2011-10-03 13:49:53 +053036
37 /* Multi-Purpose Pins Functionality configuration */
Albert ARIBAUD4d424312012-11-26 11:27:36 +000038 static const u32 kwmpp_config[] = {
Jason Cooper8d038fa2011-10-03 13:49:53 +053039 MPP0_SPI_SCn, /* SPI Flash */
40 MPP1_SPI_MOSI,
41 MPP2_SPI_SCK,
42 MPP3_SPI_MISO,
43 MPP4_NF_IO6,
44 MPP5_NF_IO7,
45 MPP6_SYSRST_OUTn,
46 MPP7_GPO,
47 MPP8_TW_SDA,
48 MPP9_TW_SCK,
49 MPP10_UART0_TXD, /* Serial */
50 MPP11_UART0_RXD,
51 MPP12_SD_CLK, /* SDIO Slot */
52 MPP13_SD_CMD,
53 MPP14_SD_D0,
54 MPP15_SD_D1,
55 MPP16_SD_D2,
56 MPP17_SD_D3,
57 MPP18_NF_IO0,
58 MPP19_NF_IO1,
59 MPP20_GE1_0, /* Gigabit Ethernet */
60 MPP21_GE1_1,
61 MPP22_GE1_2,
62 MPP23_GE1_3,
63 MPP24_GE1_4,
64 MPP25_GE1_5,
65 MPP26_GE1_6,
66 MPP27_GE1_7,
67 MPP28_GE1_8,
68 MPP29_GE1_9,
69 MPP30_GE1_10,
70 MPP31_GE1_11,
71 MPP32_GE1_12,
72 MPP33_GE1_13,
73 MPP34_GE1_14,
74 MPP35_GE1_15,
75 MPP36_GPIO, /* 7 external GPIO pins (36 - 45) */
76 MPP37_GPIO,
77 MPP38_GPIO,
78 MPP39_GPIO,
79 MPP40_TDM_SPI_SCK,
80 MPP41_TDM_SPI_MISO,
81 MPP42_TDM_SPI_MOSI,
82 MPP43_GPIO,
83 MPP44_GPIO,
84 MPP45_GPIO,
85 MPP46_GPIO,
86 MPP47_GPIO, /* Bluetooth LED */
87 MPP48_GPIO, /* Wifi LED */
88 MPP49_GPIO, /* Wifi AP LED */
89 0
90 };
Valentin Longchamp7d0d5022012-06-01 01:31:00 +000091 kirkwood_mpp_conf(kwmpp_config, NULL);
Jason Cooper8d038fa2011-10-03 13:49:53 +053092 return 0;
93}
94
Tony Dinh179dd642022-01-30 15:02:30 -080095int board_eth_init(struct bd_info *bis)
Jason Cooper8d038fa2011-10-03 13:49:53 +053096{
Tony Dinh179dd642022-01-30 15:02:30 -080097 return cpu_eth_init(bis);
Jason Cooper8d038fa2011-10-03 13:49:53 +053098}
99
Tony Dinh179dd642022-01-30 15:02:30 -0800100int board_init(void)
Jason Cooper8d038fa2011-10-03 13:49:53 +0530101{
Tony Dinh179dd642022-01-30 15:02:30 -0800102 /* address of boot parameters */
103 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
Tony Dinh4cd94772021-07-25 23:01:19 -0700104
Tony Dinh179dd642022-01-30 15:02:30 -0800105 return 0;
Jason Cooper8d038fa2011-10-03 13:49:53 +0530106}