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git01.mediatek.com / filogic / uboot / ba97201101698957e875825679182bae72d63b38 / . / doc / README.dk1s10_mldk20
blob: fcf8170d66607f49147b839438572b2e3cd70a3f [file] [log] [blame]
wdenkc0bc2e12004-02-09 23:12:24 +0000[diff] [blame]1
2TODO: specify IDE i/f
3
4
5===============================================================================
6 C P U , M E M O R Y , I N / O U T C O M P O N E N T S
7===============================================================================
8see also [1]-[5]
9
10CPU: "LDK2"
11 32 bit NIOS for 75 MHz
12 512 Byte for register file (30 levels)
13 with out instruction cache
14 with out data cache
15 2 KByte On Chip ROM with GERMS boot monitor
16 with out On Chip RAM
17 MSTEP multiplier
18 no Debug Core
19 no On Chip Instrumentation (OCI)
20
21 U-Boot CFG: CFG_NIOS_CPU_CLK = 75000000
22 CFG_NIOS_CPU_ICACHE = (not present)
23 CFG_NIOS_CPU_DCACHE = (not present)
24 CFG_NIOS_CPU_REG_NUMS = 512
25 CFG_NIOS_CPU_MUL = 0
26 CFG_NIOS_CPU_MSTEP = 1
27 CFG_NIOS_CPU_DBG_CORE = 0
28
29IRQ: Nr. | used by
30 ------+--------------------------------------------------------
31 16 | TIMER0 | CFG_NIOS_CPU_TIMER0_IRQ = 16
32 17 | UART0 | CFG_NIOS_CPU_UART0_IRQ = 17
33 18 | UART1 | CFG_NIOS_CPU_UART1_IRQ = 18
34 20 | LAN91C111 | CFG_NIOS_CPU_LAN0_IRQ = 20
35 25 | IDE0 | CFG_NIOS_CPU_IDE0_IRQ = 25
36
37MEMORY: 8 MByte Flash
38 16 MByte SDRAM
39
40Timer: TIMER0: high priority programmable timer (IRQ16)
41
42 U-Boot CFG: CFG_NIOS_CPU_TICK_TIMER = 0
43 CFG_NIOS_CPU_USER_TIMER = (not present)
44
45PIO: Nr. | description
46 ------+--------------------------------------------------------
47 PIO0 | CFPOWER: 1 output to controll CF power supply
48 PIO1 | BUTTON: 4 inputs for user push buttons (no IRQ)
49 ------+--------------------------------------------------------
50 not | LCD: 11 in/outputs for ASCII LCD
51 pres.| LED: 8 outputs for user LEDs
52 | SEVENSEG: 16 outputs for user seven segment display
53 | RECONF: 1 in/output for . . . . . . . . . . . .
54 | CFPRESENT: 1 input for CF present event (IRQ35)
55 | CFATASEL: 1 output to controll CF ATA card select
56
57 U-Boot CFG: CFG_NIOS_CPU_BUTTON_PIO = 1
58 CFG_NIOS_CPU_LCD_PIO = (not present)
59 CFG_NIOS_CPU_LED_PIO = (not present)
60 CFG_NIOS_CPU_SEVENSEG_PIO = (not present)
61 CFG_NIOS_CPU_RECONF_PIO = (not present)
62 CFG_NIOS_CPU_CFPRESENT_PIO = (not present)
63 CFG_NIOS_CPU_CFPOWER_PIO = 0
64 CFG_NIOS_CPU_CFATASEL_PIO = (not present)
65
66UART: UART0: fixed baudrate of 115200, fixed protocol 8N2,
67 without handshake RTS/CTS (IRQ17)
68 UART1: fixed baudrate of 115200, fixed protocol 8N1,
69 without handshake RTS/CTS (IRQ18)
70
71LAN: SMsC LAN91C111 with:
72 - offset 0x300 (LAN91C111_REGISTERS_OFFSET)
73 - data bus width 32 bit (LAN91C111_DATA_BUS_WIDTH)
74
75IDE: (TODO)
76
77
78===============================================================================
79 M E M O R Y M A P
80===============================================================================
81
82- - - - - - - - - - - external memory - - - - - - - - - - - - - - - - - - -
83
84 0x02000000 ---32-----------16|15------------0- CFG_NIOS_CPU_STACK
85 0x02000000 --+32-----------16|15------------0+
86 | . | \ \
87 | . | | |
88 | . | | > stack area
89 | . | | |
90 | . | | V
91 | . | |
92 | . | |
93 SDRAM | . | > CFG_NIOS_CPU_SDRAM_SIZE
94 | . | | = 0x01000000
95 | . | |
96 0x01000100 |- - - - - - - - - - - - - - - -+-|-
97 | . | | \
98 | . | | |
99 | . | | > CFG_NIOS_CPU_VEC_SIZE
100 | . | | | = 0x00000100
101 | | / /
102 0x01000000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_VEC_BASE
103 0x01000000 ---32-----------16|15------------0- CFG_NIOS_CPU_SDRAM_BASE
104 | sector 127 | \
105 + 0x7f0000 |- - - - - - - - - - - - - - - -| |
106 | : | |
107 Flash |- - - - : - - - -| > CFG_NIOS_CPU_FLASH_SIZE
108 | sector 1 : | | = 0x00800000
109 + 0x010000 |- - - - - - - - - - - - - - - -| |
110 | sector 0 (size = 0x10000) | /
111 0x00800000 ---8-------------4|3-------------0- CFG_NIOS_CPU_FLASH_BASE
112 | |
113 : gap :
114 : :
115
116- - - - - - - - - - - external i/o - - - - - - - - - - - - - - - - - - -
117
118 : :
119 : gap :
120 | |
121 0x00020000 ---32-----------16|15------------0-
122 | gap | \
123 0x00010310 --+-------------------------------| |
124 | | |
125 | register bank (size = 0x10) | |
126 | +--------.---.---.--- | |
127 | | bank 0 \ 1 \ 2 \ 3 \ | |
128 | |---------------------------+ | |
129 LAN91C111 | | BANK | RESERVED | | |
130 | |- - - - - - -|- - - - - - -| | > na_enet_size
131 | | RPCR | MIR | | | = 0x00010000
132 | |- - - - - - -|- - - - - - -| | |
133 | | COUNTER | RCR | | |
134 | |- - - - - - -|- - - - - - -| | |
135 | | EPH STATUS | TCR | | |
136 | +---------------------------+ | |
137 0x00010300 --+--LAN91C111_REGISTERS_OFFSET---| |
138 | gap | /
139 0x00010000 ---32-----------16|15------------0- CFG_NIOS_CPU_LAN0_BASE
140 | |
141 : gap :
142 : :
143
144- - - - - - - - - - - on chip i/o - - - - - - - - - - - - - - - - - - -
145
146 : :
147 : gap :
148 | |
149 0x00000980 ---32-----------16|15------------0-
150 | | | \
151 : (real size : : |
152 IDE i/f : and content : : > 0x00000080
153 [5] : unknown) : : |
154 | | | /
155 0x00000900 ---32-----------16|15------------0- CFG_NIOS_CPU_IDE0
156 | | \
157 : gap : > (space for PIO4..7)
158 | | /
159 0x000008c0 ---32-----------16|15------------0-
160 | (unused) | \
161 + 0x1c |- - - - - - - - - - - - - - - -| |
162 | (unused) | |
163 + 0x18 |- - - - - - - - - - - - - - - -| |
164 | (unused) | |
165 + 0x14 |- - - - - - - - - - - - - - - -| |
166 UART1 | (unused) | > 0x00000020
167 [2] + 0x10 |- - - - - - - - - - - - - - - -| |
168 | control (10 bit) (rw) | |
169 + 0x0c |- - - - - - - - - - - - - - - -| |
170 | status (10 bit) (rw) | |
171 + 0x08 |- - - - - - - - - - - - - - - -| |
172 | txdata (8 bit) (wo) | |
173 + 0x04 |- - - - - - - - - - - - - - - -| |
174 | rxdata (8 bit) (ro) | /
175 0x000008a0 ---32-----------16|15------------0- CFG_NIOS_CPU_UART1
176 | | \
177 : gap : > (space for PIO2..3)
178 | | /
179 0x00000880 ---32-----------16|15------------0-
180 | edgecapture (4 bit) (rw) | \
181 + 0x0c |- - - - - - - - - - - - - - - -| |
182 PIO1 | interruptmask (4 bit) (rw) | |
183 [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
184 | (unused) | |
185 + 0x04 |- - - - - - - - - - - - - - - -| |
186 | data (4 bit) (ro) | /
187 0x00000870 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO1
188 | (unused) | \
189 + 0x0c |- - - - - - - - - - - - - - - -| |
190 PIO0 | (unused) | |
191 [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
192 | (unused) | |
193 + 0x04 |- - - - - - - - - - - - - - - -| |
194 | data (1 bit) (wo) | /
195 0x00000860 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO0
196 | (unused) | \
197 + 0x1c |- - - - - - - - - - - - - - - -| |
198 | (unused) | |
199 + 0x18 |- - - - - - - - - - - - - - - -| |
200 | snaph (16 bit) (rw) | |
201 + 0x14 |- - - - - - - - - - - - - - - -| |
202 TIMER0 | snapl (16 bit) (rw) | |
203 [3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020
204 | periodh (16 bit) (rw) | |
205 + 0x0c |- - - - - - - - - - - - - - - -| |
206 | periodl (16 bit) (rw) | |
207 + 0x08 |- - - - - - - - - - - - - - - -| |
208 | control (4 bit) (rw) | |
209 + 0x04 |- - - - - - - - - - - - - - - -| |
210 | status (2 bit) (rw) | /
211 0x00000840 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER0
212 | | \
213 : gap : > (space for UART2)
214 | | /
215 0x00000820 ---32-----------16|15------------0-
216 | (unused) | \
217 + 0x1c |- - - - - - - - - - - - - - - -| |
218 | (unused) | |
219 + 0x18 |- - - - - - - - - - - - - - - -| |
220 | (unused) | |
221 + 0x14 |- - - - - - - - - - - - - - - -| |
222 UART0 | (unused) | > 0x00000020
223 [2] + 0x10 |- - - - - - - - - - - - - - - -| |
224 | control (10 bit) (rw) | |
225 + 0x0c |- - - - - - - - - - - - - - - -| |
226 | status (10 bit) (rw) | |
227 + 0x08 |- - - - - - - - - - - - - - - -| |
228 | txdata (8 bit) (wo) | |
229 + 0x04 |- - - - - - - - - - - - - - - -| |
230 | rxdata (8 bit) (ro) | /
231 0x00000800 ---32-----------16|15------------0- CFG_NIOS_CPU_UART0
232
233- - - - - - - - - - - on chip memory 1 - - - - - - - - - - -
234
235 0x00000800 ---32-----------16|15------------0-
236 | : | \
237 | : | |
238 GERMS | : | > CFG_NIOS_CPU_ROM_SIZE
239 | : | | = 0x00000800
240 | : | /
241 0x00000000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_RST_VECT
242 0x00000000 ---32-----------16|15------------0- CFG_NIOS_CPU_ROM_BASE
243
244===============================================================================
245 F L A S H M E M O R Y A L L O C A T I O N
246===============================================================================
247
248 0x01000000 ---8-------------4|3-------------0-
249 | : | \
250 SAFE | : | > 1 MByte
251 FPGA conf. | : | / (NOT usable by software)
252 0x00f00000 --+- - - - - - - -:- - - - - - - -+-
253 | : | \
254 USER | : | > 1 MByte
255 FPGA conf. | : | / (NOT usable by software)
256 0x00e00000 --+- - - - - - - -:- - - - - - - -+-
257 | : | \
258 | : | |
259 WEB pages | : | > 2 MByte
260 | : | | (provisory usable)
261 | : | /
262 0x00c00000 --+- - - - - - - -:- - - - - - - -+-
263 | : | \
264 | : | |
265 | : | |
266 | : | > 4 MByte free for use
267 | : | |
268 0x00840000 --+- - - - - - - -:- - - - - - - -+-|- u-boot environment
269 | : | /
270 0x00800000 |- - - - - - - -:- - - - - - - -+- - u-boot _start()
271 0x00800000 ---8-------------4|3-------------0-
272
273
274===============================================================================
275 R E F E R E N C E S
276===============================================================================
277[1] http://www.altera.com/literature/manual/mnl_nios_board_stratix_1s10.pdf
278[2] http://www.altera.com/literature/ds/ds_nios_uart.pdf
279[3] http://www.altera.com/literature/ds/ds_nios_timer.pdf
280[4] http://www.altera.com/literature/ds/ds_nios_pio.pdf
281[5] http://www.opencores.org/projects/ata/
282 http://www.t13.org/index.html
283
284
285===============================================================================
286Stephan Linz <linz@li-pro.net>