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Alifer Moraesa0a29482020-03-06 07:46:33 -03001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2020 NXP
4 */
5
6#ifndef __IMX8M_PHANBELL_H
7#define __IMX8M_PHANBELL_H
8
9#include <linux/sizes.h>
10#include <asm/arch/imx-regs.h>
11
12#define CONFIG_SPL_MAX_SIZE (172 * 1024)
13#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
14#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
15#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
Alifer Moraesa0a29482020-03-06 07:46:33 -030016
17#ifdef CONFIG_SPL_BUILD
18/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
19#define CONFIG_SPL_WATCHDOG_SUPPORT
20#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
21#define CONFIG_SPL_POWER_SUPPORT
22#define CONFIG_SPL_I2C_SUPPORT
23#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
24#define CONFIG_SPL_STACK 0x187FF0
25#define CONFIG_SPL_LIBCOMMON_SUPPORT
26#define CONFIG_SPL_LIBGENERIC_SUPPORT
27#define CONFIG_SPL_GPIO_SUPPORT
28#define CONFIG_SPL_MMC_SUPPORT
29#define CONFIG_SPL_BSS_START_ADDR 0x00180000
30#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
31#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
32#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
33#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
34
35/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
36#define CONFIG_MALLOC_F_ADDR 0x182000
37/* For RAW image gives a error info not panic */
38#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
39
40#undef CONFIG_DM_MMC
41#undef CONFIG_DM_PMIC
42#undef CONFIG_DM_PMIC_PFUZE100
43
44#define CONFIG_SYS_I2C
45#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
46#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
47#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
48
49#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
50
51#define CONFIG_POWER
52#define CONFIG_POWER_I2C
53#endif
54
55#define CONFIG_REMAKE_ELF
56
Alifer Moraesa0a29482020-03-06 07:46:33 -030057/* ENET Config */
58/* ENET1 */
59#if defined(CONFIG_CMD_NET)
Alifer Moraesa0a29482020-03-06 07:46:33 -030060#define CONFIG_MII
61#define CONFIG_ETHPRIME "FEC"
62
63#define CONFIG_FEC_MXC
64#define CONFIG_FEC_XCV_TYPE RGMII
65#define CONFIG_FEC_MXC_PHYADDR 0
66#define FEC_QUIRK_ENET_MAC
67
68#define CONFIG_PHY_GIGE
69#define IMX_FEC_BASE 0x30BE0000
70
71#define CONFIG_PHYLIB
72#endif
73
74#define CONFIG_MFG_ENV_SETTINGS \
75 "initrd_addr=0x43800000\0" \
76 "initrd_high=0xffffffff\0" \
77
78/* Initial environment variables */
79#define CONFIG_EXTRA_ENV_SETTINGS \
80 CONFIG_MFG_ENV_SETTINGS \
81 "script=boot.scr\0" \
82 "image=Image\0" \
83 "console=ttymxc0,115200\0" \
84 "fdt_addr=0x43000000\0" \
85 "fdt_high=0xffffffffffffffff\0" \
86 "boot_fdt=try\0" \
87 "fdt_file=imx8mq-phanbell.dtb\0" \
88 "initrd_addr=0x43800000\0" \
89 "initrd_high=0xffffffffffffffff\0" \
90 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
91 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
92 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
93 "mmcautodetect=yes\0" \
94 "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
95 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
96 "bootscript=echo Running bootscript from mmc ...; " \
97 "source\0" \
98 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
99 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
100 "mmcboot=echo Booting from mmc ...; " \
101 "run mmcargs; " \
102 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
103 "if run loadfdt; then " \
104 "booti ${loadaddr} - ${fdt_addr}; " \
105 "else " \
106 "echo WARN: Cannot load the DT; " \
107 "fi; " \
108 "else " \
109 "echo wait for boot; " \
110 "fi;\0" \
111 "netargs=setenv bootargs console=${console} " \
112 "root=/dev/nfs " \
113 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
114 "netboot=echo Booting from net ...; " \
115 "run netargs; " \
116 "if test ${ip_dyn} = yes; then " \
117 "setenv get_cmd dhcp; " \
118 "else " \
119 "setenv get_cmd tftp; " \
120 "fi; " \
121 "${get_cmd} ${loadaddr} ${image}; " \
122 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
123 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
124 "booti ${loadaddr} - ${fdt_addr}; " \
125 "else " \
126 "echo WARN: Cannot load the DT; " \
127 "fi; " \
128 "else " \
129 "booti; " \
130 "fi;\0"
131
132#define CONFIG_BOOTCOMMAND \
133 "mmc dev ${mmcdev}; if mmc rescan; then " \
134 "if run loadbootscript; then " \
135 "run bootscript; " \
136 "else " \
137 "if run loadimage; then " \
138 "run mmcboot; " \
139 "else run netboot; " \
140 "fi; " \
141 "fi; " \
142 "else booti ${loadaddr} - ${fdt_addr}; fi"
143
144/* Link Definitions */
145#define CONFIG_LOADADDR 0x40480000
146
147#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
148
149#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
150#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
151#define CONFIG_SYS_INIT_SP_OFFSET \
152 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
153#define CONFIG_SYS_INIT_SP_ADDR \
154 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
155
Alifer Moraesa0a29482020-03-06 07:46:33 -0300156#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
157
158/* Size of malloc() pool */
159#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024)
160
161#define CONFIG_SYS_SDRAM_BASE 0x40000000
162#define PHYS_SDRAM 0x40000000
163#define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */
164
165#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
166#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
167 (PHYS_SDRAM_SIZE >> 1))
168
Alifer Moraesa0a29482020-03-06 07:46:33 -0300169#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
170
171/* Monitor Command Prompt */
172#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
173#define CONFIG_SYS_CBSIZE 1024
174#define CONFIG_SYS_MAXARGS 64
175#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
176#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
177 sizeof(CONFIG_SYS_PROMPT) + 16)
178
179#define CONFIG_IMX_BOOTAUX
180
Alifer Moraesa0a29482020-03-06 07:46:33 -0300181#define CONFIG_SYS_FSL_USDHC_NUM 2
182#define CONFIG_SYS_FSL_ESDHC_ADDR 0
183
184#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
185
186#define CONFIG_MXC_GPIO
187
Alifer Moraesa0a29482020-03-06 07:46:33 -0300188/* I2C Configs */
189#define CONFIG_SYS_I2C_SPEED 100000
190
191#define CONFIG_OF_SYSTEM_SETUP
192
193#ifndef CONFIG_SPL_BUILD
194#define CONFIG_DM_PMIC
195#endif
196
197#endif