Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2008 |
| 3 | * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de. |
| 4 | * |
Wolfgang Denk | bd8ec7e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | /************************************************************************ |
| 9 | * quad100hd.h - configuration for Quad100hd board |
| 10 | ***********************************************************************/ |
| 11 | #ifndef __CONFIG_H |
| 12 | #define __CONFIG_H |
| 13 | |
| 14 | /*----------------------------------------------------------------------- |
| 15 | * High Level Configuration Options |
| 16 | *----------------------------------------------------------------------*/ |
| 17 | #define CONFIG_QUAD100HD 1 /* Board is Quad100hd */ |
| 18 | #define CONFIG_4xx 1 /* ... PPC4xx family */ |
| 19 | #define CONFIG_405EP 1 /* Specifc 405EP support*/ |
| 20 | |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 21 | #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 |
| 22 | |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 23 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ |
| 24 | |
| 25 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
| 26 | |
| 27 | #define PLLMR0_DEFAULT PLLMR0_266_133_66 /* no PCI */ |
| 28 | #define PLLMR1_DEFAULT PLLMR1_266_133_66 /* no PCI */ |
| 29 | |
Gary Jennejohn | f605570 | 2008-05-14 13:39:22 +0200 | [diff] [blame] | 30 | /* the environment is in the EEPROM by default */ |
Jean-Christophe PLAGNIOL-VILLARD | e46af64 | 2008-09-05 09:19:30 +0200 | [diff] [blame] | 31 | #define CONFIG_ENV_IS_IN_EEPROM |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 32 | #undef CONFIG_ENV_IS_IN_FLASH |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 33 | |
Ben Warren | 3a918a6 | 2008-10-27 23:50:15 -0700 | [diff] [blame] | 34 | #define CONFIG_PPC4xx_EMAC |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 35 | #define CONFIG_HAS_ETH1 1 |
| 36 | #define CONFIG_MII 1 /* MII PHY management */ |
| 37 | #define CONFIG_PHY_ADDR 0x01 /* PHY address */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 38 | #define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 39 | #define CONFIG_PHY_RESET 1 |
| 40 | #define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ |
| 41 | |
| 42 | /* |
| 43 | * Command line configuration. |
| 44 | */ |
| 45 | #include <config_cmd_default.h> |
| 46 | |
| 47 | #undef CONFIG_CMD_ASKENV |
| 48 | #undef CONFIG_CMD_CACHE |
| 49 | #define CONFIG_CMD_DHCP |
| 50 | #undef CONFIG_CMD_DIAG |
| 51 | #define CONFIG_CMD_EEPROM |
| 52 | #undef CONFIG_CMD_ELF |
| 53 | #define CONFIG_CMD_I2C |
| 54 | #undef CONFIG_CMD_IRQ |
| 55 | #define CONFIG_CMD_JFFS2 |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 56 | #undef CONFIG_CMD_MII |
| 57 | #define CONFIG_CMD_NAND |
| 58 | #undef CONFIG_CMD_PING |
| 59 | #define CONFIG_CMD_REGINFO |
| 60 | |
| 61 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 62 | |
| 63 | /*----------------------------------------------------------------------- |
| 64 | * SDRAM |
| 65 | *----------------------------------------------------------------------*/ |
| 66 | /* |
| 67 | * SDRAM configuration (please see cpu/ppc/sdram.[ch]) |
| 68 | */ |
| 69 | #define CONFIG_SDRAM_BANK0 1 |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 70 | |
| 71 | /* FIX! SDRAM timings used in datasheet */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 72 | #define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */ |
| 73 | #define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */ |
| 74 | #define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */ |
| 75 | #define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ |
| 76 | #define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */ |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 77 | |
| 78 | /* |
| 79 | * JFFS2 |
| 80 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 81 | #define CONFIG_SYS_JFFS2_FIRST_BANK 0 |
| 82 | #ifdef CONFIG_SYS_KERNEL_IN_JFFS2 |
| 83 | #define CONFIG_SYS_JFFS2_FIRST_SECTOR 0 /* JFFS starts at block 0 */ |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 84 | #else /* kernel not in JFFS */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 85 | #define CONFIG_SYS_JFFS2_FIRST_SECTOR 8 /* block 0-7 is kernel (1MB = 8 sectors) */ |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 86 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 87 | #define CONFIG_SYS_JFFS2_NUM_BANKS 1 |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 88 | |
| 89 | /*----------------------------------------------------------------------- |
| 90 | * Serial Port |
| 91 | *----------------------------------------------------------------------*/ |
Stefan Roese | 3ddce57 | 2010-09-20 16:05:31 +0200 | [diff] [blame] | 92 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
| 93 | #define CONFIG_SYS_NS16550 |
| 94 | #define CONFIG_SYS_NS16550_SERIAL |
| 95 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 96 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 97 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ |
| 98 | #define CONFIG_SYS_BASE_BAUD 691200 |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 99 | #define CONFIG_BAUDRATE 115200 |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 100 | |
| 101 | /* The following table includes the supported baudrates */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 102 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 103 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} |
| 104 | |
| 105 | /*----------------------------------------------------------------------- |
| 106 | * Miscellaneous configurable options |
| 107 | *----------------------------------------------------------------------*/ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 108 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 109 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 110 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 111 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 112 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 113 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 114 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 115 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 116 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 117 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 118 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
| 119 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 120 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 121 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
| 122 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */ |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 123 | |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 124 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 125 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 126 | |
| 127 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
| 128 | #define CONFIG_LOOPW 1 /* enable loopw command */ |
| 129 | #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ |
| 130 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
| 131 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
| 132 | |
| 133 | /*----------------------------------------------------------------------- |
| 134 | * I2C |
| 135 | *----------------------------------------------------------------------*/ |
Dirk Eibach | 42b204f | 2013-04-25 02:40:01 +0000 | [diff] [blame] | 136 | #define CONFIG_SYS_I2C |
| 137 | #define CONFIG_SYS_I2C_PPC4XX |
| 138 | #define CONFIG_SYS_I2C_PPC4XX_CH0 |
| 139 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 |
| 140 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 141 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 142 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ |
| 143 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* bytes of address */ |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 144 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 145 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 8 byte write page size */ |
| 146 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
| 147 | #define CONFIG_SYS_EEPROM_SIZE 0x2000 |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 148 | |
| 149 | /*----------------------------------------------------------------------- |
| 150 | * Start addresses for the final memory configuration |
| 151 | * (Set up by the startup code) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 152 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 153 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 154 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 155 | #define CONFIG_SYS_FLASH_BASE 0xFFC00000 |
| 156 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ |
| 157 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 158 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE) |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 159 | |
| 160 | /* |
| 161 | * For booting Linux, the board info and command line data |
| 162 | * have to be in the first 8 MB of memory, since this is |
| 163 | * the maximum mapped by the Linux kernel during initialization. |
| 164 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 165 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 166 | |
| 167 | /*----------------------------------------------------------------------- |
| 168 | * FLASH organization |
| 169 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 170 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
Jean-Christophe PLAGNIOL-VILLARD | 8d94c23 | 2008-08-13 01:40:42 +0200 | [diff] [blame] | 171 | #define CONFIG_FLASH_CFI_DRIVER |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 172 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 173 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 174 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 175 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| 176 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 177 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 178 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 179 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 180 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 181 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
| 182 | #define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */ |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 183 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 184 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
| 185 | #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 186 | |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 187 | #ifdef CONFIG_ENV_IS_IN_FLASH |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 188 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ |
Gary Jennejohn | f605570 | 2008-05-14 13:39:22 +0200 | [diff] [blame] | 189 | /* the environment is located before u-boot */ |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 190 | #define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE) |
Gary Jennejohn | f605570 | 2008-05-14 13:39:22 +0200 | [diff] [blame] | 191 | |
| 192 | /* Address and size of Redundant Environment Sector */ |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 193 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) |
| 194 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 195 | #endif |
| 196 | |
Jean-Christophe PLAGNIOL-VILLARD | e46af64 | 2008-09-05 09:19:30 +0200 | [diff] [blame] | 197 | #ifdef CONFIG_ENV_IS_IN_EEPROM |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 198 | #define CONFIG_ENV_SIZE 0x400 /* Size of Environment vars */ |
| 199 | #define CONFIG_ENV_OFFSET 0x00000000 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 200 | #define CONFIG_SYS_ENABLE_CRC_16 1 /* Intrinsyc formatting used crc16 */ |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 201 | #endif |
| 202 | |
| 203 | /* partly from PPCBoot */ |
| 204 | /* NAND */ |
| 205 | #define CONFIG_NAND |
| 206 | #ifdef CONFIG_NAND |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 207 | #define CONFIG_SYS_NAND_BASE 0x60000000 |
| 208 | #define CONFIG_SYS_NAND_CS 10 /* our CS is GPIO10 */ |
| 209 | #define CONFIG_SYS_NAND_RDY 23 /* our RDY is GPIO23 */ |
| 210 | #define CONFIG_SYS_NAND_CE 24 /* our CE is GPIO24 */ |
| 211 | #define CONFIG_SYS_NAND_CLE 31 /* our CLE is GPIO31 */ |
| 212 | #define CONFIG_SYS_NAND_ALE 30 /* our ALE is GPIO30 */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 213 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
Wolfgang Denk | 25ded72 | 2009-07-18 15:32:10 +0200 | [diff] [blame] | 214 | |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 215 | #endif |
| 216 | |
| 217 | /*----------------------------------------------------------------------- |
| 218 | * Definitions for initial stack pointer and data area (in data cache) |
| 219 | */ |
| 220 | /* use on chip memory (OCM) for temperary stack until sdram is tested */ |
Stefan Roese | 88fbf93 | 2010-04-15 16:07:28 +0200 | [diff] [blame] | 221 | /* see ./arch/powerpc/cpu/ppc4xx/start.S */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 222 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 223 | |
| 224 | /* On Chip Memory location */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 225 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
| 226 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 |
| 227 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM */ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 228 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 229 | |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 230 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 231 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 232 | |
| 233 | /*----------------------------------------------------------------------- |
| 234 | * External Bus Controller (EBC) Setup |
| 235 | * Taken from PPCBoot board/icecube/icecube.h |
| 236 | */ |
| 237 | |
Stefan Roese | 88fbf93 | 2010-04-15 16:07:28 +0200 | [diff] [blame] | 238 | /* see ./arch/powerpc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 239 | #define CONFIG_SYS_EBC_PB0AP 0x04002480 |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 240 | /* AMD NOR flash - this corresponds to FLASH_BASE so may be correct */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 241 | #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 |
| 242 | #define CONFIG_SYS_EBC_PB1AP 0x04005480 |
| 243 | #define CONFIG_SYS_EBC_PB1CR 0x60018000 |
| 244 | #define CONFIG_SYS_EBC_PB2AP 0x00000000 |
| 245 | #define CONFIG_SYS_EBC_PB2CR 0x00000000 |
| 246 | #define CONFIG_SYS_EBC_PB3AP 0x00000000 |
| 247 | #define CONFIG_SYS_EBC_PB3CR 0x00000000 |
| 248 | #define CONFIG_SYS_EBC_PB4AP 0x00000000 |
| 249 | #define CONFIG_SYS_EBC_PB4CR 0x00000000 |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 250 | |
| 251 | /*----------------------------------------------------------------------- |
| 252 | * Definitions for GPIO setup (PPC405EP specific) |
| 253 | * |
| 254 | * Taken in part from PPCBoot board/icecube/icecube.h |
| 255 | */ |
Stefan Roese | 88fbf93 | 2010-04-15 16:07:28 +0200 | [diff] [blame] | 256 | /* see ./arch/powerpc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */ |
Stefan Roese | 8cb251a | 2010-09-12 06:21:37 +0200 | [diff] [blame] | 257 | #define CONFIG_SYS_GPIO0_OSRL 0x55555550 |
| 258 | #define CONFIG_SYS_GPIO0_OSRH 0x00000110 |
| 259 | #define CONFIG_SYS_GPIO0_ISR1L 0x00000000 |
| 260 | #define CONFIG_SYS_GPIO0_ISR1H 0x15555445 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 261 | #define CONFIG_SYS_GPIO0_TSRL 0x00000000 |
Stefan Roese | 8cb251a | 2010-09-12 06:21:37 +0200 | [diff] [blame] | 262 | #define CONFIG_SYS_GPIO0_TSRH 0x00000000 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 263 | #define CONFIG_SYS_GPIO0_TCR 0xFFFF8097 |
| 264 | #define CONFIG_SYS_GPIO0_ODR 0x00000000 |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 265 | |
| 266 | #if defined(CONFIG_CMD_KGDB) |
| 267 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
Gary Jennejohn | 0ec4f30 | 2008-04-28 14:04:32 +0200 | [diff] [blame] | 268 | #endif |
| 269 | |
| 270 | /* ENVIRONMENT VARS */ |
| 271 | |
| 272 | #define CONFIG_IPADDR 192.168.1.67 |
| 273 | #define CONFIG_SERVERIP 192.168.1.50 |
| 274 | #define CONFIG_GATEWAYIP 192.168.1.1 |
| 275 | #define CONFIG_NETMASK 255.255.255.0 |
| 276 | #define CONFIG_LOADADDR 300000 |
| 277 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
| 278 | |
| 279 | /* pass open firmware flat tree */ |
| 280 | #define CONFIG_OF_LIBFDT 1 |
| 281 | |
| 282 | #endif /* __CONFIG_H */ |