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git01.mediatek.com / filogic / uboot / ba64b8b30bebfda159aff96ce41534e09b25bc3a / . / arch / arm / mach-imx / misc.c
blob: 31e95a9a28899a3e7ff7e7df733940cf9fc8ee6b [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Stefan Roese05b0ef42013-04-09 21:06:08 +0000[diff] [blame]2/*
3 * Copyright 2013 Stefan Roese <sr@denx.de>
Stefan Roese05b0ef42013-04-09 21:06:08 +0000[diff] [blame]4 */
5
6#include <common.h>
Jeroen Hofstee1abf3a12014-10-08 22:57:52 +0200[diff] [blame]7#include <asm/arch/sys_proto.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +0900[diff] [blame]8#include <linux/errno.h>
Stefan Roese05b0ef42013-04-09 21:06:08 +0000[diff] [blame]9#include <asm/io.h>
Stefano Babic33731bc2017-06-29 10:16:06 +0200[diff] [blame]10#include <asm/mach-imx/regs-common.h>
Stefan Roese05b0ef42013-04-09 21:06:08 +0000[diff] [blame]11
Ye Life96e152019-01-04 09:10:20 +0000[diff] [blame]12DECLARE_GLOBAL_DATA_PTR;
13
Stefan Roese05b0ef42013-04-09 21:06:08 +0000[diff] [blame]14/* 1 second delay should be plenty of time for block reset. */
15#define RESET_MAX_TIMEOUT 1000000
16
17#define MXS_BLOCK_SFTRST (1 << 31)
18#define MXS_BLOCK_CLKGATE (1 << 30)
19
20int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
21 int timeout)
22{
23 while (--timeout) {
24 if ((readl(&reg->reg) & mask) == mask)
25 break;
26 udelay(1);
27 }
28
29 return !timeout;
30}
31
32int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
33 int timeout)
34{
35 while (--timeout) {
36 if ((readl(&reg->reg) & mask) == 0)
37 break;
38 udelay(1);
39 }
40
41 return !timeout;
42}
43
44int mxs_reset_block(struct mxs_register_32 *reg)
45{
46 /* Clear SFTRST */
47 writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
48
49 if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
50 return 1;
51
52 /* Clear CLKGATE */
53 writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
54
55 /* Set SFTRST */
56 writel(MXS_BLOCK_SFTRST, &reg->reg_set);
57
58 /* Wait for CLKGATE being set */
59 if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
60 return 1;
61
62 /* Clear SFTRST */
63 writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
64
65 if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
66 return 1;
67
68 /* Clear CLKGATE */
69 writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
70
71 if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
72 return 1;
73
74 return 0;
75}
Ye Life96e152019-01-04 09:10:20 +0000[diff] [blame]76
77static ulong get_sp(void)
78{
79 ulong ret;
80
81 asm("mov %0, sp" : "=r"(ret) : );
82 return ret;
83}
84
85void board_lmb_reserve(struct lmb *lmb)
86{
87 ulong sp, bank_end;
88 int bank;
89
90 sp = get_sp();
91 debug("## Current stack ends at 0x%08lx ", sp);
92
93 /* adjust sp by 16K to be safe */
94 sp -= 4096 << 2;
95 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
96 if (sp < gd->bd->bi_dram[bank].start)
97 continue;
98 bank_end = gd->bd->bi_dram[bank].start +
99 gd->bd->bi_dram[bank].size;
100 if (sp >= bank_end)
101 continue;
102 lmb_reserve(lmb, sp, bank_end - sp);
103 break;
104 }
105}