blob: 58ead45941c5c9b795c007551f90126964b87790 [file] [log] [blame]
Teresa Remmet30fb74d2021-01-13 16:28:09 +01001/* SPDX-License-Identifier: GPL-2.0-or-later
2 *
3 * Copyright (C) 2020 PHYTEC Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de>
5 */
6
7#ifndef __PHYCORE_IMX8MP_H
8#define __PHYCORE_IMX8MP_H
9
10#include <linux/sizes.h>
11#include <asm/arch/imx-regs.h>
12
13#define CONFIG_SYS_BOOTM_LEN SZ_64M
14
15#define CONFIG_SPL_MAX_SIZE (152 * SZ_1K)
16#define CONFIG_SYS_MONITOR_LEN SZ_512K
17#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
18#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
19#define CONFIG_SYS_UBOOT_BASE \
20 (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
21
22#ifdef CONFIG_SPL_BUILD
23#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
24#define CONFIG_SPL_STACK 0x960000
25#define CONFIG_SPL_BSS_START_ADDR 0x98FC00
26#define CONFIG_SPL_BSS_MAX_SIZE SZ_1K
27#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
28#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
29
30#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
31
32#define CONFIG_POWER
33#define CONFIG_POWER_I2C
34#define CONFIG_POWER_PCA9450
35
Simon Glass0529b592021-07-10 21:14:32 -060036#define CONFIG_SYS_I2C_LEGACY
Teresa Remmet30fb74d2021-01-13 16:28:09 +010037
38#endif
39
40#define CONFIG_EXTRA_ENV_SETTINGS \
41 "image=Image\0" \
Teresa Remmet5fc6abf2021-07-07 12:57:59 +000042 "console=ttymxc0,115200\0" \
Teresa Remmet30fb74d2021-01-13 16:28:09 +010043 "fdt_addr=0x48000000\0" \
44 "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
Teresa Remmet7de60a62021-07-07 12:58:00 +000045 "ip_dyn=yes\0" \
Teresa Remmet30fb74d2021-01-13 16:28:09 +010046 "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
47 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
48 "mmcroot=2\0" \
49 "mmcautodetect=yes\0" \
50 "mmcargs=setenv bootargs console=${console} " \
51 "root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \
52 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
53 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
54 "mmcboot=echo Booting from mmc ...; " \
55 "run mmcargs; " \
56 "if run loadfdt; then " \
57 "booti ${loadaddr} - ${fdt_addr}; " \
58 "else " \
59 "echo WARN: Cannot load the DT; " \
60 "fi;\0 " \
Teresa Remmet7de60a62021-07-07 12:58:00 +000061 "nfsroot=/nfs\0" \
62 "netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp " \
63 "nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
64 "netboot=echo Booting from net ...; " \
65 "run netargs; " \
66 "if test ${ip_dyn} = yes; then " \
67 "setenv get_cmd dhcp; " \
68 "else " \
69 "setenv get_cmd tftp; " \
70 "fi; " \
71 "${get_cmd} ${loadaddr} ${image}; " \
72 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
73 "booti ${loadaddr} - ${fdt_addr}; " \
74 "else " \
75 "echo WARN: Cannot load the DT; " \
76 "fi;\0" \
Teresa Remmet30fb74d2021-01-13 16:28:09 +010077
78#define CONFIG_BOOTCOMMAND \
79 "mmc dev ${mmcdev}; if mmc rescan; then " \
80 "if run loadimage; then " \
81 "run mmcboot; " \
82 "else run netboot; " \
83 "fi; " \
84 "fi;"
85
86/* Link Definitions */
87#define CONFIG_LOADADDR 0x40480000
88#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
89
90#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
91#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
92#define CONFIG_SYS_INIT_SP_OFFSET \
93 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
94#define CONFIG_SYS_INIT_SP_ADDR \
95 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
96
97#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */
98
99/* Size of malloc() pool */
100#define CONFIG_SYS_MALLOC_LEN SZ_32M
101#define CONFIG_SYS_SDRAM_BASE 0x40000000
102
103#define PHYS_SDRAM 0x40000000
104#define PHYS_SDRAM_SIZE 0x80000000
105
106/* UART */
Teresa Remmet5fc6abf2021-07-07 12:57:59 +0000107#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100108
109/* Monitor Command Prompt */
110#define CONFIG_SYS_CBSIZE SZ_2K
111#define CONFIG_SYS_MAXARGS 64
112#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
113
114/* USDHC */
115#define CONFIG_FSL_USDHC
116#define CONFIG_SYS_FSL_USDHC_NUM 2
117#define CONFIG_SYS_FSL_ESDHC_ADDR 0
118#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
119
120/* I2C */
121#define CONFIG_SYS_I2C_SPEED 100000
122
123#endif /* __PHYCORE_IMX8MP_H */