blob: ecc88ba43746f52f8f8bae78cca0a98c5fa0d924 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Kumar Gala6bf7e462010-12-15 04:52:48 -06002/*
3 * Copyright 2010 Freescale Semiconductor, Inc.
Kumar Gala6bf7e462010-12-15 04:52:48 -06004 */
5
6#include <config.h>
7#include <common.h>
Simon Glass0f2af882020-05-10 11:40:05 -06008#include <log.h>
Kumar Gala6bf7e462010-12-15 04:52:48 -06009#include <asm/io.h>
10#include <asm/immap_86xx.h>
11#include <asm/fsl_serdes.h>
12
13#define SRDS1_MAX_LANES 4
14#define SRDS2_MAX_LANES 4
15
16static u32 serdes1_prtcl_map, serdes2_prtcl_map;
17
18static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
19 [0x1] = {PCIE1, PCIE1, PCIE1, PCIE1},
20 [0x4] = {PCIE1, PCIE1, PCIE1, PCIE1},
21 [0x7] = {NONE, NONE, NONE, NONE},
22};
23
24static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
25 [0x0] = {PCIE2, PCIE2, PCIE2, PCIE2},
26 [0x4] = {PCIE2, PCIE2, PCIE2, PCIE2},
27 [0x7] = {NONE, NONE, NONE, NONE},
28};
29
30int is_serdes_configured(enum srds_prtcl device)
31{
Hou Zhiqiangb435ae92016-08-02 19:03:22 +080032 int ret;
33
34 if (!(serdes1_prtcl_map & (1 << NONE)))
35 fsl_serdes_init();
36
37 ret = (1 << device) & serdes1_prtcl_map;
Kumar Gala6bf7e462010-12-15 04:52:48 -060038
39 if (ret)
40 return ret;
41
Hou Zhiqiangb435ae92016-08-02 19:03:22 +080042 if (!(serdes2_prtcl_map & (1 << NONE)))
43 fsl_serdes_init();
44
Kumar Gala6bf7e462010-12-15 04:52:48 -060045 return (1 << device) & serdes2_prtcl_map;
46}
47
48void fsl_serdes_init(void)
49{
50 immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
51 ccsr_gur_t *gur = &immap->im_gur;
52 u32 pordevsr = in_be32(&gur->pordevsr);
53 u32 srds_cfg = (pordevsr & MPC8610_PORDEVSR_IO_SEL) >>
54 MPC8610_PORDEVSR_IO_SEL_SHIFT;
55 int lane;
56
Hou Zhiqiangb435ae92016-08-02 19:03:22 +080057 if (serdes1_prtcl_map & (1 << NONE) &&
58 serdes2_prtcl_map & (1 << NONE))
59 return;
60
Kumar Gala6bf7e462010-12-15 04:52:48 -060061 debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
62
Axel Linab95b092013-05-26 15:00:30 +080063 if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
Kumar Gala6bf7e462010-12-15 04:52:48 -060064 printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
65 return;
66 }
67 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
68 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
69 serdes1_prtcl_map |= (1 << lane_prtcl);
70 }
71
Hou Zhiqiangb435ae92016-08-02 19:03:22 +080072 /* Set the first bit to indicate serdes has been initialized */
73 serdes1_prtcl_map |= (1 << NONE);
74
Axel Linab95b092013-05-26 15:00:30 +080075 if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
Kumar Gala6bf7e462010-12-15 04:52:48 -060076 printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
77 return;
78 }
79
80 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
81 enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
82 serdes2_prtcl_map |= (1 << lane_prtcl);
83 }
Hou Zhiqiangb435ae92016-08-02 19:03:22 +080084
85 /* Set the first bit to indicate serdes has been initialized */
86 serdes2_prtcl_map |= (1 << NONE);
Kumar Gala6bf7e462010-12-15 04:52:48 -060087}