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git01.mediatek.com / filogic / uboot / ba3b893435e07fc4a8050477a25552abd4db72a2 / . / board / htkw / mcx / mcx.h
blob: 0d4c642203440e70b1e9d236cf6fec4c1c98eda7 [file] [log] [blame]
Ilya Yanok37651282012-02-07 23:30:22 +0000[diff] [blame]1/*
2 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
3 *
4 * Based on ti/evm/evm.h
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.
19 */
20
21#ifndef _AM3517EVM_H_
22#define _AM3517EVM_H_
23
24const omap3_sysinfo sysinfo = {
25 DDR_DISCRETE,
26 "HTKW mcx Board",
27 "NAND",
28};
29
30/*
31 * IEN - Input Enable
32 * IDIS - Input Disable
33 * PTD - Pull type Down
34 * PTU - Pull type Up
35 * DIS - Pull type selection is inactive
36 * EN - Pull type selection is active
37 * M0 - Mode 0
38 * The commented string gives the final mux configuration for that pin
39 */
40#define MUX_MCX() \
41 /* SDRC */\
42 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
43 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
44 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
45 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
46 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
47 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
48 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
49 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
50 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
51 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
52 MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
53 MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
54 MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
55 MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
56 MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
57 MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
58 MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
59 MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
60 MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
61 MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
62 MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
63 MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
64 MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
65 MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
66 MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
67 MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
68 MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
69 MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
70 MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
71 MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
72 MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
73 MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
74 MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
75 MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
76 MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
77 MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
78 MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
79 MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
80 MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
81 MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
82 MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
83 MUX_VAL(CP(SDRC_CKE0), (M0)) \
84 MUX_VAL(CP(SDRC_CKE1), (M0)) \
85 MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
86 /*sdrc_strben_dly0*/\
87 MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
88 /*sdrc_strben_dly1*/\
89 /* GPMC */\
90 MUX_VAL(CP(GPMC_A1), (IEN | PTU | EN | M4)) \
91 MUX_VAL(CP(GPMC_A2), (IEN | PTU | EN | M4)) \
92 MUX_VAL(CP(GPMC_A3), (IEN | PTU | EN | M4)) \
93 MUX_VAL(CP(GPMC_A4), (IEN | PTU | EN | M4)) \
94 MUX_VAL(CP(GPMC_A5), (IEN | PTU | EN | M4)) \
95 MUX_VAL(CP(GPMC_A6), (IEN | PTU | EN | M4)) \
96 MUX_VAL(CP(GPMC_A7), (IEN | PTU | EN | M4)) \
97 MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4)) \
98 MUX_VAL(CP(GPMC_A9), (IEN | PTU | EN | M4)) \
Stefano Babic72c72122012-10-16 04:07:04 +0000[diff] [blame]99 MUX_VAL(CP(GPMC_A10), (IEN | PTU | EN | M4)) \
Ilya Yanok37651282012-02-07 23:30:22 +0000[diff] [blame]100 /* GPIO_43 LCD buffer enable */ \
101 MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
102 MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
103 MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
104 MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
105 MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
106 MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
107 MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
108 MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
109 MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
110 MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
111 MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
112 MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
113 MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
114 MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
115 MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
116 MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
117 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
118 MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M4)) \
119 MUX_VAL(CP(GPMC_NCS2), (IEN | PTU | EN | M4)) \
120 MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) \
121 MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4))\
122 MUX_VAL(CP(GPMC_NCS5), (IEN | PTU | EN | M4)) \
123 MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M4)) \
124 /* GPIO_57 TS_PenIRQn */\
125 MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)) \
126 /* GPIO_58 ETHERNET RESET */\
127 MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)) \
128 MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
129 MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
130 MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
131 MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
132 MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | DIS | M4)) \
133 /* GPIO_61 SD-CARD CD */ \
134 MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | EN | M4)) \
135 /* GPIO_62 Nand write protect, keep enabled */ \
136 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
137 MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4))\
138 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4))\
139 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \
140 /* GPIO_65 SD-CARD WP */\
141 /* DSS */\
142 MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
143 MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
144 MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
145 MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
Stefano Babiceccb5762012-10-16 04:07:03 +0000[diff] [blame]146 MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \
147 MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \
148 MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \
Ilya Yanok37651282012-02-07 23:30:22 +0000[diff] [blame]149 MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
150 MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
151 MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
152 MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
153 MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
Stefano Babiceccb5762012-10-16 04:07:03 +0000[diff] [blame]154 MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \
155 MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \
Ilya Yanok37651282012-02-07 23:30:22 +0000[diff] [blame]156 MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
157 MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
158 MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
159 MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
160 MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
Stefano Babiceccb5762012-10-16 04:07:03 +0000[diff] [blame]161 MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \
162 MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \
163 MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \
164 MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
Ilya Yanok37651282012-02-07 23:30:22 +0000[diff] [blame]165 MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
166 MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
Stefano Babiceccb5762012-10-16 04:07:03 +0000[diff] [blame]167 MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
Ilya Yanok37651282012-02-07 23:30:22 +0000[diff] [blame]168 MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
169 MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
170 /* CAMERA */\
171 MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M4)) \
172 MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M4)) \
173 MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | EN | M4)) \
174 MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M4)) \
175 MUX_VAL(CP(CAM_FLD), (IEN | PTD | EN | M4)) \
176 MUX_VAL(CP(CAM_D0), (IEN | PTD | EN | M4)) \
177 MUX_VAL(CP(CAM_D1), (IEN | PTD | EN | M4)) \
178 MUX_VAL(CP(CAM_D2), (IEN | PTD | EN | M4)) \
179 MUX_VAL(CP(CAM_D3), (IEN | PTD | EN | M4)) \
180 MUX_VAL(CP(CAM_D4), (IEN | PTD | EN | M4)) \
181 MUX_VAL(CP(CAM_D5), (IEN | PTD | EN | M4)) \
182 MUX_VAL(CP(CAM_D6), (IEN | PTD | EN | M4)) \
183 MUX_VAL(CP(CAM_D7), (IEN | PTD | EN | M4)) \
184 MUX_VAL(CP(CAM_D8), (IEN | PTD | EN | M4)) \
185 MUX_VAL(CP(CAM_D9), (IEN | PTD | EN | M4)) \
186 MUX_VAL(CP(CAM_D10), (IEN | PTD | EN | M4)) \
187 MUX_VAL(CP(CAM_D11), (IEN | PTD | EN | M4)) \
188 MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | EN | M4)) \
189 MUX_VAL(CP(CAM_WEN), (IEN | PTD | EN | M4)) \
190 MUX_VAL(CP(CAM_STROBE), (IEN | PTD | EN | M4)) \
191 MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) \
192 MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) \
193 MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) \
194 MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) \
195 /* MMC */\
196 MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
197 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
198 MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
199 MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
200 MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
201 MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
202 MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
203 MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
204 MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
205 MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
206 \
207 MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M4)) \
208 MUX_VAL(CP(MMC2_CMD), (IDIS | PTD | DIS | M4)) \
209 /* GPIO_131 LCD Enable */ \
210 MUX_VAL(CP(MMC2_DAT0), (IDIS | PTD | DIS | M4)) \
211 /* GPIO_132 USB host Enable */\
212 MUX_VAL(CP(MMC2_DAT1), (IDIS | PTD | DIS | M4)) \
213 /* GPIO_133 HDMI PD */\
214 MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) \
215 MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4))\
216 /* McBSP */\
217 MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
218 MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
219 MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
220 MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
221 MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
222 MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
223 MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
224 \
225 MUX_VAL(CP(MCBSP2_FSX), (IEN | PTU | EN | M4))\
226 MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTU | EN | M4)) \
227 MUX_VAL(CP(MCBSP2_DR), (IEN | PTU | EN | M4)) \
228 MUX_VAL(CP(MCBSP2_DX), (IEN | PTU | EN | M4))\
229 \
230 MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \
231 MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \
232 MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \
233 MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4))\
234 \
235 MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) \
236 /* GPIO_152 USB phy2 reset */\
237 MUX_VAL(CP(MCBSP4_DR), (IEN | PTU | EN | M4)) \
238 /* GPIO_153 */\
239 MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) \
240 /* GPIO_154 USB phy1 reset */\
241 MUX_VAL(CP(MCBSP4_FSX), (IEN | PTU | EN | M4)) \
242 /* GPIO_155 TS_BUSY */\
243 /* UART */\
244 MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
245 MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \
246 MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \
247 MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
248 \
249 MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
250 MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
251 MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
252 MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
253 \
254 MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \
255 MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \
256 MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
257 MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
258 /* I2C */\
259 MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
260 MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
261 MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
262 MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
263 MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
264 MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
265 MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
266 MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
Stefano Babic756a7bf2012-10-20 23:56:07 +0000[diff] [blame]267 MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M4)) \
268 /* GPIO_170 Touchscreen ISR */\
Ilya Yanok37651282012-02-07 23:30:22 +0000[diff] [blame]269 /* McSPI */\
270 MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
271 MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
272 MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
273 MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
274 MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | EN | M4)) \
275 MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | EN | M4)) \
276 MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | EN | M4)) \
277 MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) \
278 /* HSUSB2_dat7 */\
279 MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) \
280 /* HSUSB2_dat4 */\
281 MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) \
282 /* HSUSB2_dat5 */\
283 MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) \
284 /* HSUSB2_dat6 */\
285 MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) \
286 /* HSUSB2_dat3 */\
287 /* CCDC */\
288 MUX_VAL(CP(CCDC_PCLK), (IEN | PTD | EN | M4)) \
Stefano Babicbc6c8b82012-06-13 22:34:42 +0000[diff] [blame]289 /* CCDC_FIELD: gpio_95, uP-TXD4 */ \
290 MUX_VAL(CP(CCDC_FIELD), (IDIS | PTD | DIS | M2)) \
291 /* CCDC_HD: gpio_96, uP-RTS4# */ \
292 MUX_VAL(CP(CCDC_HD), (IDIS | PTD | DIS | M2)) \
293 /* CCDC_VD: gpio_97, uP-CTS4# */ \
294 MUX_VAL(CP(CCDC_VD), (IEN | PTD | EN | M2)) \
295 /* CCDC_WEN: gpio_98, uP-RXD4 */ \
296 MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M2)) \
Ilya Yanok37651282012-02-07 23:30:22 +0000[diff] [blame]297 MUX_VAL(CP(CCDC_WEN), (IEN | PTD | EN | M4)) \
298 MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | EN | M4)) \
299 MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | EN | M4)) \
300 MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | EN | M4)) \
301 MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | EN | M4)) \
302 MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | EN | M4)) \
303 MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | EN | M4)) \
304 MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | EN | M4)) \
305 MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | EN | M4)) \
306 /* RMII */\
307 MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
308 MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
309 MUX_VAL(CP(RMII_RXD0), (IEN | PTD | M0)) \
310 MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
311 MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
312 MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
313 MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
314 MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
315 MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
316 MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
317 /* HECC */\
Stefano Babiceccb5762012-10-16 04:07:03 +0000[diff] [blame]318 MUX_VAL(CP(HECC1_TXD), (IEN | PTD | EN | M0)) \
319 MUX_VAL(CP(HECC1_RXD), (IEN | PTD | EN | M0)) \
Ilya Yanok37651282012-02-07 23:30:22 +0000[diff] [blame]320 /* HSUSB */\
321 MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
Stefano Babiceccb5762012-10-16 04:07:03 +0000[diff] [blame]322 MUX_VAL(CP(HSUSB0_STP), (IEN | PTU | DIS | M0)) \
Ilya Yanok37651282012-02-07 23:30:22 +0000[diff] [blame]323 MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
324 MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \
325 MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
326 MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
327 MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
328 MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
329 MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
330 MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
331 MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
332 MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
333 MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
334 /* HDQ */\
335 MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \
336 /* Control and debug */\
337 MUX_VAL(CP(SYS_32K), (IEN | PTD | EN | M4)) \
338 MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
339 MUX_VAL(CP(SYS_NIRQ), (IEN | PTD | EN | M4)) \
340 MUX_VAL(CP(SYS_NRESWARM), (IEN | PTU | DIS | M4)) \
341 /* SYS_nRESWARM */\
342 MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) \
343 MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) \
344 MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) \
345 MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) \
346 MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) \
347 MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4))\
348 MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4))\
349 MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | DIS | M4)) \
350 MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | DIS | M4)) \
351 \
352 MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
353 MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))\
354 MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4))\
355 /* JTAG */\
356 MUX_VAL(CP(JTAG_nTRST), (IEN | PTU | EN | M4)) \
357 MUX_VAL(CP(JTAG_TCK), (IEN | PTU | EN | M4)) \
358 MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M4)) \
359 MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M4)) \
360 MUX_VAL(CP(JTAG_EMU0), (IEN | PTU | EN | M4)) \
361 MUX_VAL(CP(JTAG_EMU1), (IEN | PTU | EN | M4))\
362 /* ETK (ES2 onwards) */\
363 MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \
364 /* hsusb1_stp */ \
365 MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \
366 /* hsusb1_clk */\
367 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)) \
368 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)) \
369 MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)) \
370 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)) \
371 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)) \
372 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)) \
373 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)) \
374 MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)) \
375 MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \
376 MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \
377 MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M4)) \
378 MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M4)) \
379 MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M4)) \
380 MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M4)) \
381 MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \
382 MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \
383 /* Die to Die */\
384 MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
385 MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
386 MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
387 MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
388 MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
389 MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
390 MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
391 MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
392 MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
393 MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
394 MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
395 MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
396 MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
397 MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
398 MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
399 MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
400 MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
401 MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
402 MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
403 MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
404 MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
405 MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
406 MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
407 MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
408 MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
409 MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
410 MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
411 MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
412 MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
413 MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \
414
415#endif