blob: 680f6560f25780897fa01792464066bc320ab5c8 [file] [log] [blame]
Chandan Nath7d744102011-10-14 02:58:26 +00001/*
2 * mux.c
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
Tom Rini7a247722012-07-31 10:50:01 -070016#include <common.h>
17#include <asm/arch/sys_proto.h>
Chandan Nath7d744102011-10-14 02:58:26 +000018#include <asm/arch/hardware.h>
Peter Korsgaard5d3f6822012-10-18 01:21:11 +000019#include <asm/arch/mux.h>
Chandan Nath7d744102011-10-14 02:58:26 +000020#include <asm/io.h>
Tom Rini184fffa2012-08-08 09:03:07 -070021#include <i2c.h>
Peter Korsgaard85ec2db2012-10-18 01:21:09 +000022#include "board.h"
Chandan Nath7d744102011-10-14 02:58:26 +000023
Chandan Nath7d744102011-10-14 02:58:26 +000024static struct module_pin_mux uart0_pin_mux[] = {
25 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
26 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
27 {-1},
28};
29
Andrew Bradford65c51ff2012-10-25 08:21:30 -040030static struct module_pin_mux uart1_pin_mux[] = {
31 {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
32 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
33 {-1},
34};
35
36static struct module_pin_mux uart2_pin_mux[] = {
37 {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
38 {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
39 {-1},
40};
41
42static struct module_pin_mux uart3_pin_mux[] = {
43 {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
44 {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
45 {-1},
46};
47
48static struct module_pin_mux uart4_pin_mux[] = {
49 {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
50 {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
51 {-1},
52};
53
54static struct module_pin_mux uart5_pin_mux[] = {
55 {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
56 {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
57 {-1},
58};
59
Chandan Nathd6e97f82012-01-09 20:38:58 +000060static struct module_pin_mux mmc0_pin_mux[] = {
61 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
62 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
63 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
64 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
65 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
66 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
67 {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
68 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
69 {-1},
70};
Tom Rini7a247722012-07-31 10:50:01 -070071
Matthias Fuchs63ffc5a2012-11-02 03:35:59 +000072static struct module_pin_mux mmc0_no_cd_pin_mux[] = {
73 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
74 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
75 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
76 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
77 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
78 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
79 {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
80 {-1},
81};
82
Tom Rini7a247722012-07-31 10:50:01 -070083static struct module_pin_mux mmc0_pin_mux_sk_evm[] = {
84 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
85 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
86 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
87 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
88 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
89 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
90 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
91 {-1},
92};
Chandan Nathd6e97f82012-01-09 20:38:58 +000093
Tom Rini9670a1e2012-08-08 10:32:09 -070094static struct module_pin_mux mmc1_pin_mux[] = {
95 {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
96 {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
97 {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
98 {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
99 {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
100 {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
101 {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
102 {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_CD */
103 {-1},
104};
105
Patil, Rachna5f70c512012-01-22 23:47:01 +0000106static struct module_pin_mux i2c0_pin_mux[] = {
107 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
108 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
109 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
110 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
111 {-1},
112};
113
Steve Sakoman695b1fe2012-06-22 07:45:57 +0000114static struct module_pin_mux i2c1_pin_mux[] = {
115 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
116 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
117 {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
118 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
119 {-1},
120};
121
Tom Rini883401e2012-08-08 14:35:55 -0700122static struct module_pin_mux spi0_pin_mux[] = {
123 {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */
124 {OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
125 PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */
126 {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */
127 {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
128 PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */
129 {-1},
130};
131
Tom Rini4b302402012-07-31 08:55:01 -0700132static struct module_pin_mux gpio0_7_pin_mux[] = {
133 {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */
134 {-1},
135};
136
Chandan Nathb79a12e2012-07-24 12:22:18 +0000137static struct module_pin_mux rgmii1_pin_mux[] = {
138 {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
139 {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
140 {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
141 {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
142 {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
143 {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
144 {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
145 {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
146 {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
147 {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
148 {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
149 {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
150 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
151 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
152 {-1},
153};
154
155static struct module_pin_mux mii1_pin_mux[] = {
156 {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
157 {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
158 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
159 {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
160 {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
161 {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
162 {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
163 {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
164 {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
165 {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
166 {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
167 {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
168 {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
169 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
170 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
171 {-1},
172};
173
pekon gupta2badbde2014-07-22 16:03:20 +0530174#ifdef CONFIG_NAND
Ilya Yanokfd056552012-11-06 13:06:29 +0000175static struct module_pin_mux nand_pin_mux[] = {
pekon gupta2badbde2014-07-22 16:03:20 +0530176 {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */
177 {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */
178 {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */
179 {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */
180 {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */
181 {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */
182 {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */
183 {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */
184#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
185 {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */
186 {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */
187 {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
188 {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */
189 {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */
190 {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */
191 {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */
192 {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */
193#endif
194 {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */
195 {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* nWP */
196 {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* nCS */
197 {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* WEN */
198 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* OE */
199 {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* ADV_ALE */
200 {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */
Ilya Yanokfd056552012-11-06 13:06:29 +0000201 {-1},
202};
pekon gupta0efbdcf2014-07-22 16:03:21 +0530203#elif defined(CONFIG_NOR)
Steve Kipiszbe9b6f82013-07-18 15:13:03 -0400204static struct module_pin_mux bone_norcape_pin_mux[] = {
pekon gupta0efbdcf2014-07-22 16:03:21 +0530205 {OFFSET(gpmc_a0), MODE(0) | PULLUDDIS}, /* NOR_A0 */
206 {OFFSET(gpmc_a1), MODE(0) | PULLUDDIS}, /* NOR_A1 */
207 {OFFSET(gpmc_a2), MODE(0) | PULLUDDIS}, /* NOR_A2 */
208 {OFFSET(gpmc_a3), MODE(0) | PULLUDDIS}, /* NOR_A3 */
209 {OFFSET(gpmc_a4), MODE(0) | PULLUDDIS}, /* NOR_A4 */
210 {OFFSET(gpmc_a5), MODE(0) | PULLUDDIS}, /* NOR_A5 */
211 {OFFSET(gpmc_a6), MODE(0) | PULLUDDIS}, /* NOR_A6 */
212 {OFFSET(gpmc_a7), MODE(0) | PULLUDDIS}, /* NOR_A7 */
213 {OFFSET(gpmc_ad0), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD0 */
214 {OFFSET(gpmc_ad1), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD1 */
215 {OFFSET(gpmc_ad2), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD2 */
216 {OFFSET(gpmc_ad3), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD3 */
217 {OFFSET(gpmc_ad4), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD4 */
218 {OFFSET(gpmc_ad5), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD5 */
219 {OFFSET(gpmc_ad6), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD6 */
220 {OFFSET(gpmc_ad7), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD7 */
221 {OFFSET(gpmc_ad8), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD8 */
222 {OFFSET(gpmc_ad9), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD9 */
223 {OFFSET(gpmc_ad10), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD10 */
224 {OFFSET(gpmc_ad11), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD11 */
225 {OFFSET(gpmc_ad12), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD12 */
226 {OFFSET(gpmc_ad13), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD13 */
227 {OFFSET(gpmc_ad14), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD14 */
228 {OFFSET(gpmc_ad15), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD15 */
229 {OFFSET(gpmc_csn0), MODE(0) | PULLUDEN | PULLUP_EN}, /* CE */
230 {OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* ALE */
231 {OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN | PULLDOWN_EN},/* OEn_REN */
232 {OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN | PULLDOWN_EN},/* unused */
233 {OFFSET(gpmc_wen), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* WEN */
234 {OFFSET(gpmc_wait0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},/*WAIT*/
Steve Kipiszbe9b6f82013-07-18 15:13:03 -0400235 {-1},
236};
237#endif
238
Heiko Schocherb21f2ac2013-07-30 10:48:54 +0530239#if defined(CONFIG_NOR_BOOT)
Heiko Schocherb21f2ac2013-07-30 10:48:54 +0530240void enable_norboot_pin_mux(void)
241{
pekon gupta0efbdcf2014-07-22 16:03:21 +0530242 configure_module_pin_mux(bone_norcape_pin_mux);
Heiko Schocherb21f2ac2013-07-30 10:48:54 +0530243}
244#endif
Steve Kipiszbe9b6f82013-07-18 15:13:03 -0400245
Chandan Nath7d744102011-10-14 02:58:26 +0000246void enable_uart0_pin_mux(void)
247{
248 configure_module_pin_mux(uart0_pin_mux);
249}
Chandan Nathd6e97f82012-01-09 20:38:58 +0000250
Andrew Bradford65c51ff2012-10-25 08:21:30 -0400251void enable_uart1_pin_mux(void)
252{
253 configure_module_pin_mux(uart1_pin_mux);
254}
255
256void enable_uart2_pin_mux(void)
257{
258 configure_module_pin_mux(uart2_pin_mux);
259}
260
261void enable_uart3_pin_mux(void)
262{
263 configure_module_pin_mux(uart3_pin_mux);
264}
265
266void enable_uart4_pin_mux(void)
267{
268 configure_module_pin_mux(uart4_pin_mux);
269}
270
271void enable_uart5_pin_mux(void)
272{
273 configure_module_pin_mux(uart5_pin_mux);
274}
Patil, Rachna5f70c512012-01-22 23:47:01 +0000275
276void enable_i2c0_pin_mux(void)
277{
278 configure_module_pin_mux(i2c0_pin_mux);
279}
Steve Sakoman695b1fe2012-06-22 07:45:57 +0000280
Tom Rini184fffa2012-08-08 09:03:07 -0700281/*
282 * The AM335x GP EVM, if daughter card(s) are connected, can have 8
283 * different profiles. These profiles determine what peripherals are
284 * valid and need pinmux to be configured.
285 */
286#define PROFILE_NONE 0x0
287#define PROFILE_0 (1 << 0)
288#define PROFILE_1 (1 << 1)
289#define PROFILE_2 (1 << 2)
290#define PROFILE_3 (1 << 3)
291#define PROFILE_4 (1 << 4)
292#define PROFILE_5 (1 << 5)
293#define PROFILE_6 (1 << 6)
294#define PROFILE_7 (1 << 7)
295#define PROFILE_MASK 0x7
296#define PROFILE_ALL 0xFF
297
298/* CPLD registers */
299#define I2C_CPLD_ADDR 0x35
300#define CFG_REG 0x10
301
302static unsigned short detect_daughter_board_profile(void)
Steve Sakoman695b1fe2012-06-22 07:45:57 +0000303{
Tom Rini184fffa2012-08-08 09:03:07 -0700304 unsigned short val;
Chandan Nathb79a12e2012-07-24 12:22:18 +0000305
Tom Rini184fffa2012-08-08 09:03:07 -0700306 if (i2c_probe(I2C_CPLD_ADDR))
307 return PROFILE_NONE;
308
309 if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2))
310 return PROFILE_NONE;
311
312 return (1 << (val & PROFILE_MASK));
313}
314
315void enable_board_pin_mux(struct am335x_baseboard_id *header)
316{
317 /* Do board-specific muxes. */
Tom Rini4021fd92013-07-18 15:13:01 -0400318 if (board_is_bone(header)) {
Tom Rini7a247722012-07-31 10:50:01 -0700319 /* Beaglebone pinmux */
Tom Rini184fffa2012-08-08 09:03:07 -0700320 configure_module_pin_mux(i2c1_pin_mux);
Tom Rini7a247722012-07-31 10:50:01 -0700321 configure_module_pin_mux(mii1_pin_mux);
322 configure_module_pin_mux(mmc0_pin_mux);
pekon gupta2badbde2014-07-22 16:03:20 +0530323#if defined(CONFIG_NAND)
324 configure_module_pin_mux(nand_pin_mux);
pekon gupta0efbdcf2014-07-22 16:03:21 +0530325#elif defined(CONFIG_NOR)
Steve Kipiszbe9b6f82013-07-18 15:13:03 -0400326 configure_module_pin_mux(bone_norcape_pin_mux);
pekon gupta2badbde2014-07-22 16:03:20 +0530327#else
328 configure_module_pin_mux(mmc1_pin_mux);
Steve Kipiszbe9b6f82013-07-18 15:13:03 -0400329#endif
Tom Rini4021fd92013-07-18 15:13:01 -0400330 } else if (board_is_gp_evm(header)) {
Tom Rini7a247722012-07-31 10:50:01 -0700331 /* General Purpose EVM */
Tom Rini184fffa2012-08-08 09:03:07 -0700332 unsigned short profile = detect_daughter_board_profile();
Tom Rini7a247722012-07-31 10:50:01 -0700333 configure_module_pin_mux(rgmii1_pin_mux);
334 configure_module_pin_mux(mmc0_pin_mux);
Tom Rini184fffa2012-08-08 09:03:07 -0700335 /* In profile #2 i2c1 and spi0 conflict. */
336 if (profile & ~PROFILE_2)
337 configure_module_pin_mux(i2c1_pin_mux);
Ilya Yanokfd056552012-11-06 13:06:29 +0000338 /* Profiles 2 & 3 don't have NAND */
pekon gupta2badbde2014-07-22 16:03:20 +0530339#ifdef CONFIG_NAND
Ilya Yanokfd056552012-11-06 13:06:29 +0000340 if (profile & ~(PROFILE_2 | PROFILE_3))
341 configure_module_pin_mux(nand_pin_mux);
pekon gupta2badbde2014-07-22 16:03:20 +0530342#endif
Tom Rini9670a1e2012-08-08 10:32:09 -0700343 else if (profile == PROFILE_2) {
344 configure_module_pin_mux(mmc1_pin_mux);
Tom Rini883401e2012-08-08 14:35:55 -0700345 configure_module_pin_mux(spi0_pin_mux);
Tom Rini9670a1e2012-08-08 10:32:09 -0700346 }
Tom Rini4021fd92013-07-18 15:13:01 -0400347 } else if (board_is_idk(header)) {
Tom Rini986d7552014-08-01 09:53:24 -0400348 /* Industrial Motor Control (IDK) */
Matthias Fuchs63ffc5a2012-11-02 03:35:59 +0000349 configure_module_pin_mux(mii1_pin_mux);
350 configure_module_pin_mux(mmc0_no_cd_pin_mux);
Tom Rini4021fd92013-07-18 15:13:01 -0400351 } else if (board_is_evm_sk(header)) {
Tom Rini7a247722012-07-31 10:50:01 -0700352 /* Starter Kit EVM */
Tom Rini184fffa2012-08-08 09:03:07 -0700353 configure_module_pin_mux(i2c1_pin_mux);
Tom Rini7a247722012-07-31 10:50:01 -0700354 configure_module_pin_mux(gpio0_7_pin_mux);
355 configure_module_pin_mux(rgmii1_pin_mux);
356 configure_module_pin_mux(mmc0_pin_mux_sk_evm);
Tom Rini4021fd92013-07-18 15:13:01 -0400357 } else if (board_is_bone_lt(header)) {
Koen Kooi95e79472012-10-23 01:56:40 +0000358 /* Beaglebone LT pinmux */
359 configure_module_pin_mux(i2c1_pin_mux);
360 configure_module_pin_mux(mii1_pin_mux);
361 configure_module_pin_mux(mmc0_pin_mux);
Tom Rinief4c4812014-10-08 17:10:27 -0400362#if defined(CONFIG_NAND) && defined(CONFIG_EMMC_BOOT)
pekon gupta2badbde2014-07-22 16:03:20 +0530363 configure_module_pin_mux(nand_pin_mux);
Tom Rinief4c4812014-10-08 17:10:27 -0400364#elif defined(CONFIG_NOR) && defined(CONFIG_EMMC_BOOT)
pekon gupta0efbdcf2014-07-22 16:03:21 +0530365 configure_module_pin_mux(bone_norcape_pin_mux);
pekon gupta2badbde2014-07-22 16:03:20 +0530366#else
Koen Kooi95e79472012-10-23 01:56:40 +0000367 configure_module_pin_mux(mmc1_pin_mux);
pekon gupta2badbde2014-07-22 16:03:20 +0530368#endif
Tom Rini7a247722012-07-31 10:50:01 -0700369 } else {
370 puts("Unknown board, cannot configure pinmux.");
371 hang();
372 }
Tom Rini4b302402012-07-31 08:55:01 -0700373}