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Stefan Roese49639682006-08-15 14:22:35 +02001/*
2 * (C) Copyright 2006
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de
4 *
Stefan Roesea1831882006-10-07 11:35:25 +02005 * (C) Copyright 2006
6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
7 *
Stefan Roese49639682006-08-15 14:22:35 +02008 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
Stefan Roese49639682006-08-15 14:22:35 +020028
Jon Loeliger145318c2007-07-09 18:38:39 -050029#if defined(CONFIG_CMD_NAND)
Stefan Roese49639682006-08-15 14:22:35 +020030
Stefan Roesea1831882006-10-07 11:35:25 +020031#include <asm/processor.h>
Stefan Roese49639682006-08-15 14:22:35 +020032#include <nand.h>
33
Stefan Roese49639682006-08-15 14:22:35 +020034struct alpr_ndfc_regs {
Stefan Roese2a4a9432006-11-27 14:12:17 +010035 u8 cmd[4];
36 u8 addr_wait;
37 u8 term;
38 u8 dummy;
39 u8 dummy2;
40 u8 data;
Stefan Roese49639682006-08-15 14:22:35 +020041};
42
43static u8 hwctl;
Stefan Roesea1831882006-10-07 11:35:25 +020044static struct alpr_ndfc_regs *alpr_ndfc = NULL;
Stefan Roese49639682006-08-15 14:22:35 +020045
Stefan Roese2a4a9432006-11-27 14:12:17 +010046#define readb(addr) (u8)(*(volatile u8 *)(addr))
47#define writeb(d,addr) *(volatile u8 *)(addr) = ((u8)(d))
Stefan Roese49639682006-08-15 14:22:35 +020048
Stefan Roese49639682006-08-15 14:22:35 +020049/*
50 * The ALPR has a NAND Flash Controller (NDFC) that handles all accesses to
51 * the NAND devices. The NDFC has command, address and data registers that
52 * when accessed will set up the NAND flash pins appropriately. We'll use the
53 * hwcontrol function to save the configuration in a global variable.
54 * We can then use this information in the read and write functions to
55 * determine which NDFC register to access.
56 *
Stefan Roesea1831882006-10-07 11:35:25 +020057 * There are 2 NAND devices on the board, a Hynix HY27US08561A (1 GByte).
Stefan Roese49639682006-08-15 14:22:35 +020058 */
William Juul52c07962007-10-31 13:53:06 +010059static void alpr_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
William Juulb76ec382007-11-08 10:39:53 +010060{
William Juul9e9c2c12007-11-09 13:32:30 +010061 struct nand_chip *this = mtd->priv;
Stefan Roese49639682006-08-15 14:22:35 +020062
William Juul52c07962007-10-31 13:53:06 +010063 if (ctrl & NAND_CTRL_CHANGE) {
64 if ( ctrl & NAND_CLE )
65 hwctl |= 0x1;
66 else
67 hwctl &= ~0x1;
68 if ( ctrl & NAND_ALE )
69 hwctl |= 0x2;
70 else
71 hwctl &= ~0x2;
72 if ( (ctrl & NAND_NCE) != NAND_NCE)
73 writeb(0x00, &(alpr_ndfc->term));
74 }
75 if (cmd != NAND_CMD_NONE)
76 writeb(cmd, this->IO_ADDR_W);
Stefan Roese49639682006-08-15 14:22:35 +020077}
78
Stefan Roesea1831882006-10-07 11:35:25 +020079static u_char alpr_nand_read_byte(struct mtd_info *mtd)
Stefan Roese49639682006-08-15 14:22:35 +020080{
Stefan Roesea1831882006-10-07 11:35:25 +020081 return readb(&(alpr_ndfc->data));
Stefan Roese49639682006-08-15 14:22:35 +020082}
83
Stefan Roesea1831882006-10-07 11:35:25 +020084static void alpr_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
Stefan Roese49639682006-08-15 14:22:35 +020085{
Stefan Roesea1831882006-10-07 11:35:25 +020086 struct nand_chip *nand = mtd->priv;
Stefan Roese49639682006-08-15 14:22:35 +020087 int i;
88
Stefan Roese49639682006-08-15 14:22:35 +020089 for (i = 0; i < len; i++) {
90 if (hwctl & 0x1)
Stefan Roesea1831882006-10-07 11:35:25 +020091 /*
92 * IO_ADDR_W used as CMD[i] reg to support multiple NAND
93 * chips.
94 */
95 writeb(buf[i], nand->IO_ADDR_W);
96 else if (hwctl & 0x2)
97 writeb(buf[i], &(alpr_ndfc->addr_wait));
98 else
99 writeb(buf[i], &(alpr_ndfc->data));
Stefan Roese49639682006-08-15 14:22:35 +0200100 }
101}
102
Stefan Roesea1831882006-10-07 11:35:25 +0200103static void alpr_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
Stefan Roese49639682006-08-15 14:22:35 +0200104{
105 int i;
106
107 for (i = 0; i < len; i++) {
Stefan Roesea1831882006-10-07 11:35:25 +0200108 buf[i] = readb(&(alpr_ndfc->data));
Stefan Roese49639682006-08-15 14:22:35 +0200109 }
110}
111
Stefan Roesea1831882006-10-07 11:35:25 +0200112static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
Stefan Roese49639682006-08-15 14:22:35 +0200113{
114 int i;
115
116 for (i = 0; i < len; i++)
Stefan Roesea1831882006-10-07 11:35:25 +0200117 if (buf[i] != readb(&(alpr_ndfc->data)))
Stefan Roese49639682006-08-15 14:22:35 +0200118 return i;
119
120 return 0;
121}
122
Stefan Roesea1831882006-10-07 11:35:25 +0200123static int alpr_nand_dev_ready(struct mtd_info *mtd)
Stefan Roese49639682006-08-15 14:22:35 +0200124{
Stefan Roese49639682006-08-15 14:22:35 +0200125 volatile u_char val;
126
Stefan Roese49639682006-08-15 14:22:35 +0200127 /*
128 * Blocking read to wait for NAND to be ready
129 */
Stefan Roesea1831882006-10-07 11:35:25 +0200130 val = readb(&(alpr_ndfc->addr_wait));
Stefan Roese49639682006-08-15 14:22:35 +0200131
132 /*
133 * Return always true
134 */
135 return 1;
Stefan Roese49639682006-08-15 14:22:35 +0200136}
137
Stefan Roese1d9192f2007-01-06 15:56:13 +0100138int board_nand_init(struct nand_chip *nand)
Stefan Roese49639682006-08-15 14:22:35 +0200139{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200140 alpr_ndfc = (struct alpr_ndfc_regs *)CONFIG_SYS_NAND_BASE;
Stefan Roese49639682006-08-15 14:22:35 +0200141
William Juul52c07962007-10-31 13:53:06 +0100142 nand->ecc.mode = NAND_ECC_SOFT;
Stefan Roese49639682006-08-15 14:22:35 +0200143
Stefan Roese49639682006-08-15 14:22:35 +0200144 /* Reference hardware control function */
William Juul52c07962007-10-31 13:53:06 +0100145 nand->cmd_ctrl = alpr_nand_hwcontrol;
Stefan Roesea1831882006-10-07 11:35:25 +0200146 nand->read_byte = alpr_nand_read_byte;
147 nand->write_buf = alpr_nand_write_buf;
148 nand->read_buf = alpr_nand_read_buf;
149 nand->verify_buf = alpr_nand_verify_buf;
150 nand->dev_ready = alpr_nand_dev_ready;
Stefan Roese1d9192f2007-01-06 15:56:13 +0100151
152 return 0;
Stefan Roese49639682006-08-15 14:22:35 +0200153}
154#endif