Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2006 |
| 3 | * Heiko Schocher, DENX Software Engineering, hs@denx.de |
| 4 | * |
Stefan Roese | a183188 | 2006-10-07 11:35:25 +0200 | [diff] [blame] | 5 | * (C) Copyright 2006 |
| 6 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 7 | * |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 8 | * See file CREDITS for list of people who contributed to this |
| 9 | * project. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or |
| 12 | * modify it under the terms of the GNU General Public License as |
| 13 | * published by the Free Software Foundation; either version 2 of |
| 14 | * the License, or (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 24 | * MA 02111-1307 USA |
| 25 | */ |
| 26 | |
| 27 | #include <common.h> |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 28 | |
Jon Loeliger | 145318c | 2007-07-09 18:38:39 -0500 | [diff] [blame] | 29 | #if defined(CONFIG_CMD_NAND) |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 30 | |
Stefan Roese | a183188 | 2006-10-07 11:35:25 +0200 | [diff] [blame] | 31 | #include <asm/processor.h> |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 32 | #include <nand.h> |
| 33 | |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 34 | struct alpr_ndfc_regs { |
Stefan Roese | 2a4a943 | 2006-11-27 14:12:17 +0100 | [diff] [blame] | 35 | u8 cmd[4]; |
| 36 | u8 addr_wait; |
| 37 | u8 term; |
| 38 | u8 dummy; |
| 39 | u8 dummy2; |
| 40 | u8 data; |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 41 | }; |
| 42 | |
| 43 | static u8 hwctl; |
Stefan Roese | a183188 | 2006-10-07 11:35:25 +0200 | [diff] [blame] | 44 | static struct alpr_ndfc_regs *alpr_ndfc = NULL; |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 45 | |
Stefan Roese | 2a4a943 | 2006-11-27 14:12:17 +0100 | [diff] [blame] | 46 | #define readb(addr) (u8)(*(volatile u8 *)(addr)) |
| 47 | #define writeb(d,addr) *(volatile u8 *)(addr) = ((u8)(d)) |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 48 | |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 49 | /* |
| 50 | * The ALPR has a NAND Flash Controller (NDFC) that handles all accesses to |
| 51 | * the NAND devices. The NDFC has command, address and data registers that |
| 52 | * when accessed will set up the NAND flash pins appropriately. We'll use the |
| 53 | * hwcontrol function to save the configuration in a global variable. |
| 54 | * We can then use this information in the read and write functions to |
| 55 | * determine which NDFC register to access. |
| 56 | * |
Stefan Roese | a183188 | 2006-10-07 11:35:25 +0200 | [diff] [blame] | 57 | * There are 2 NAND devices on the board, a Hynix HY27US08561A (1 GByte). |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 58 | */ |
William Juul | 52c0796 | 2007-10-31 13:53:06 +0100 | [diff] [blame] | 59 | static void alpr_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
William Juul | b76ec38 | 2007-11-08 10:39:53 +0100 | [diff] [blame] | 60 | { |
William Juul | 9e9c2c1 | 2007-11-09 13:32:30 +0100 | [diff] [blame] | 61 | struct nand_chip *this = mtd->priv; |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 62 | |
William Juul | 52c0796 | 2007-10-31 13:53:06 +0100 | [diff] [blame] | 63 | if (ctrl & NAND_CTRL_CHANGE) { |
| 64 | if ( ctrl & NAND_CLE ) |
| 65 | hwctl |= 0x1; |
| 66 | else |
| 67 | hwctl &= ~0x1; |
| 68 | if ( ctrl & NAND_ALE ) |
| 69 | hwctl |= 0x2; |
| 70 | else |
| 71 | hwctl &= ~0x2; |
| 72 | if ( (ctrl & NAND_NCE) != NAND_NCE) |
| 73 | writeb(0x00, &(alpr_ndfc->term)); |
| 74 | } |
| 75 | if (cmd != NAND_CMD_NONE) |
| 76 | writeb(cmd, this->IO_ADDR_W); |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 77 | } |
| 78 | |
Stefan Roese | a183188 | 2006-10-07 11:35:25 +0200 | [diff] [blame] | 79 | static u_char alpr_nand_read_byte(struct mtd_info *mtd) |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 80 | { |
Stefan Roese | a183188 | 2006-10-07 11:35:25 +0200 | [diff] [blame] | 81 | return readb(&(alpr_ndfc->data)); |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 82 | } |
| 83 | |
Stefan Roese | a183188 | 2006-10-07 11:35:25 +0200 | [diff] [blame] | 84 | static void alpr_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 85 | { |
Stefan Roese | a183188 | 2006-10-07 11:35:25 +0200 | [diff] [blame] | 86 | struct nand_chip *nand = mtd->priv; |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 87 | int i; |
| 88 | |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 89 | for (i = 0; i < len; i++) { |
| 90 | if (hwctl & 0x1) |
Stefan Roese | a183188 | 2006-10-07 11:35:25 +0200 | [diff] [blame] | 91 | /* |
| 92 | * IO_ADDR_W used as CMD[i] reg to support multiple NAND |
| 93 | * chips. |
| 94 | */ |
| 95 | writeb(buf[i], nand->IO_ADDR_W); |
| 96 | else if (hwctl & 0x2) |
| 97 | writeb(buf[i], &(alpr_ndfc->addr_wait)); |
| 98 | else |
| 99 | writeb(buf[i], &(alpr_ndfc->data)); |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 100 | } |
| 101 | } |
| 102 | |
Stefan Roese | a183188 | 2006-10-07 11:35:25 +0200 | [diff] [blame] | 103 | static void alpr_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 104 | { |
| 105 | int i; |
| 106 | |
| 107 | for (i = 0; i < len; i++) { |
Stefan Roese | a183188 | 2006-10-07 11:35:25 +0200 | [diff] [blame] | 108 | buf[i] = readb(&(alpr_ndfc->data)); |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 109 | } |
| 110 | } |
| 111 | |
Stefan Roese | a183188 | 2006-10-07 11:35:25 +0200 | [diff] [blame] | 112 | static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 113 | { |
| 114 | int i; |
| 115 | |
| 116 | for (i = 0; i < len; i++) |
Stefan Roese | a183188 | 2006-10-07 11:35:25 +0200 | [diff] [blame] | 117 | if (buf[i] != readb(&(alpr_ndfc->data))) |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 118 | return i; |
| 119 | |
| 120 | return 0; |
| 121 | } |
| 122 | |
Stefan Roese | a183188 | 2006-10-07 11:35:25 +0200 | [diff] [blame] | 123 | static int alpr_nand_dev_ready(struct mtd_info *mtd) |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 124 | { |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 125 | volatile u_char val; |
| 126 | |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 127 | /* |
| 128 | * Blocking read to wait for NAND to be ready |
| 129 | */ |
Stefan Roese | a183188 | 2006-10-07 11:35:25 +0200 | [diff] [blame] | 130 | val = readb(&(alpr_ndfc->addr_wait)); |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 131 | |
| 132 | /* |
| 133 | * Return always true |
| 134 | */ |
| 135 | return 1; |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 136 | } |
| 137 | |
Stefan Roese | 1d9192f | 2007-01-06 15:56:13 +0100 | [diff] [blame] | 138 | int board_nand_init(struct nand_chip *nand) |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 139 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 140 | alpr_ndfc = (struct alpr_ndfc_regs *)CONFIG_SYS_NAND_BASE; |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 141 | |
William Juul | 52c0796 | 2007-10-31 13:53:06 +0100 | [diff] [blame] | 142 | nand->ecc.mode = NAND_ECC_SOFT; |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 143 | |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 144 | /* Reference hardware control function */ |
William Juul | 52c0796 | 2007-10-31 13:53:06 +0100 | [diff] [blame] | 145 | nand->cmd_ctrl = alpr_nand_hwcontrol; |
Stefan Roese | a183188 | 2006-10-07 11:35:25 +0200 | [diff] [blame] | 146 | nand->read_byte = alpr_nand_read_byte; |
| 147 | nand->write_buf = alpr_nand_write_buf; |
| 148 | nand->read_buf = alpr_nand_read_buf; |
| 149 | nand->verify_buf = alpr_nand_verify_buf; |
| 150 | nand->dev_ready = alpr_nand_dev_ready; |
Stefan Roese | 1d9192f | 2007-01-06 15:56:13 +0100 | [diff] [blame] | 151 | |
| 152 | return 0; |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 153 | } |
| 154 | #endif |