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wdenka445ddf2004-06-09 00:34:46 +00001 /*
wdenk13eb2212004-07-09 23:27:13 +00002 * Copyright 2004 Freescale Semiconductor.
wdenk9c53f402003-10-15 23:53:47 +00003 * (C) Copyright 2002,2003, Motorola Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
5 *
6 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27
wdenk9c53f402003-10-15 23:53:47 +000028#include <common.h>
wdenk492b9e72004-08-01 23:02:45 +000029#include <pci.h>
wdenk9c53f402003-10-15 23:53:47 +000030#include <asm/processor.h>
31#include <asm/immap_85xx.h>
32#include <spd.h>
33
Matthew McClintock148e26a2006-06-28 10:43:36 -050034#if defined(CONFIG_OF_FLAT_TREE)
35#include <ft_build.h>
Matthew McClintock148e26a2006-06-28 10:43:36 -050036#endif
37
38
Jon Loeliger77a4f6e2005-07-25 14:05:07 -050039#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
wdenk13eb2212004-07-09 23:27:13 +000040extern void ddr_enable_ecc(unsigned int dram_size);
wdenka445ddf2004-06-09 00:34:46 +000041#endif
42
wdenk13eb2212004-07-09 23:27:13 +000043extern long int spd_sdram(void);
wdenka445ddf2004-06-09 00:34:46 +000044
wdenk492b9e72004-08-01 23:02:45 +000045void local_bus_init(void);
wdenk13eb2212004-07-09 23:27:13 +000046void sdram_init(void);
47long int fixed_sdram(void);
48
wdenk9c53f402003-10-15 23:53:47 +000049
wdenkda55c6e2004-01-20 23:12:12 +000050int board_early_init_f (void)
wdenk9c53f402003-10-15 23:53:47 +000051{
wdenk492b9e72004-08-01 23:02:45 +000052 return 0;
wdenk9c53f402003-10-15 23:53:47 +000053}
54
55int checkboard (void)
56{
wdenka445ddf2004-06-09 00:34:46 +000057 puts("Board: ADS\n");
wdenk13eb2212004-07-09 23:27:13 +000058
59#ifdef CONFIG_PCI
60 printf(" PCI1: 32 bit, %d MHz (compiled)\n",
61 CONFIG_SYS_CLK_FREQ / 1000000);
62#else
63 printf(" PCI1: disabled\n");
64#endif
65
wdenk492b9e72004-08-01 23:02:45 +000066 /*
67 * Initialize local bus.
68 */
69 local_bus_init();
70
wdenka445ddf2004-06-09 00:34:46 +000071 return 0;
wdenk9c53f402003-10-15 23:53:47 +000072}
73
wdenka445ddf2004-06-09 00:34:46 +000074
wdenk13eb2212004-07-09 23:27:13 +000075long int
76initdram(int board_type)
wdenk9c53f402003-10-15 23:53:47 +000077{
78 long dram_size = 0;
79 extern long spd_sdram (void);
80 volatile immap_t *immap = (immap_t *)CFG_IMMR;
wdenk13eb2212004-07-09 23:27:13 +000081
82 puts("Initializing\n");
wdenka445ddf2004-06-09 00:34:46 +000083
wdenk9c53f402003-10-15 23:53:47 +000084#if defined(CONFIG_DDR_DLL)
wdenk13eb2212004-07-09 23:27:13 +000085 {
wdenk492b9e72004-08-01 23:02:45 +000086 volatile ccsr_gur_t *gur= &immap->im_gur;
87 uint temp_ddrdll = 0;
wdenk9c53f402003-10-15 23:53:47 +000088
wdenk492b9e72004-08-01 23:02:45 +000089 /*
90 * Work around to stabilize DDR DLL
91 */
92 temp_ddrdll = gur->ddrdllcr;
93 gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
94 asm("sync;isync;msync");
wdenk13eb2212004-07-09 23:27:13 +000095 }
wdenk9c53f402003-10-15 23:53:47 +000096#endif
97
98#if defined(CONFIG_SPD_EEPROM)
99 dram_size = spd_sdram ();
100#else
101 dram_size = fixed_sdram ();
102#endif
103
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500104#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
wdenk13eb2212004-07-09 23:27:13 +0000105 /*
106 * Initialize and enable DDR ECC.
107 */
108 ddr_enable_ecc(dram_size);
109#endif
110
111 /*
112 * Initialize SDRAM.
113 */
114 sdram_init();
115
116 puts(" DDR: ");
117 return dram_size;
118}
119
120
121/*
wdenk492b9e72004-08-01 23:02:45 +0000122 * Initialize Local Bus
wdenk13eb2212004-07-09 23:27:13 +0000123 */
124
wdenk492b9e72004-08-01 23:02:45 +0000125void
126local_bus_init(void)
wdenk13eb2212004-07-09 23:27:13 +0000127{
wdenk492b9e72004-08-01 23:02:45 +0000128 volatile immap_t *immap = (immap_t *)CFG_IMMR;
129 volatile ccsr_gur_t *gur = &immap->im_gur;
wdenk13eb2212004-07-09 23:27:13 +0000130 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
wdenk13eb2212004-07-09 23:27:13 +0000131
wdenk492b9e72004-08-01 23:02:45 +0000132 uint clkdiv;
133 uint lbc_hz;
134 sys_info_t sysinfo;
wdenk13eb2212004-07-09 23:27:13 +0000135
136 /*
wdenk492b9e72004-08-01 23:02:45 +0000137 * Errata LBC11.
138 * Fix Local Bus clock glitch when DLL is enabled.
wdenk13eb2212004-07-09 23:27:13 +0000139 *
wdenk492b9e72004-08-01 23:02:45 +0000140 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
141 * If localbus freq is > 133Mhz, DLL can be safely enabled.
142 * Between 66 and 133, the DLL is enabled with an override workaround.
wdenk13eb2212004-07-09 23:27:13 +0000143 */
wdenk492b9e72004-08-01 23:02:45 +0000144
145 get_sys_info(&sysinfo);
146 clkdiv = lbc->lcrr & 0x0f;
147 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
148
149 if (lbc_hz < 66) {
150 lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
151
152 } else if (lbc_hz >= 133) {
153 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
wdenk13eb2212004-07-09 23:27:13 +0000154
wdenk9c53f402003-10-15 23:53:47 +0000155 } else {
wdenk13eb2212004-07-09 23:27:13 +0000156 /*
157 * On REV1 boards, need to change CLKDIV before enable DLL.
158 * Default CLKDIV is 8, change it to 4 temporarily.
159 */
wdenk492b9e72004-08-01 23:02:45 +0000160 uint pvr = get_pvr();
wdenk13eb2212004-07-09 23:27:13 +0000161 uint temp_lbcdll = 0;
wdenka445ddf2004-06-09 00:34:46 +0000162
163 if (pvr == PVR_85xx_REV1) {
wdenk492b9e72004-08-01 23:02:45 +0000164 /* FIXME: Justify the high bit here. */
wdenk13eb2212004-07-09 23:27:13 +0000165 lbc->lcrr = 0x10000004;
wdenka445ddf2004-06-09 00:34:46 +0000166 }
wdenk13eb2212004-07-09 23:27:13 +0000167
wdenk492b9e72004-08-01 23:02:45 +0000168 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
169 udelay(200);
170
171 /*
172 * Sample LBC DLL ctrl reg, upshift it to set the
173 * override bits.
174 */
wdenk9c53f402003-10-15 23:53:47 +0000175 temp_lbcdll = gur->lbcdllcr;
wdenk492b9e72004-08-01 23:02:45 +0000176 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
177 asm("sync;isync;msync");
wdenk9c53f402003-10-15 23:53:47 +0000178 }
wdenk492b9e72004-08-01 23:02:45 +0000179}
180
181
182/*
183 * Initialize SDRAM memory on the Local Bus.
184 */
185
186void
187sdram_init(void)
188{
189 volatile immap_t *immap = (immap_t *)CFG_IMMR;
190 volatile ccsr_lbc_t *lbc= &immap->im_lbc;
191 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
192
193 puts(" SDRAM: ");
194 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
wdenk13eb2212004-07-09 23:27:13 +0000195
196 /*
197 * Setup SDRAM Base and Option Registers
198 */
199 lbc->or2 = CFG_OR2_PRELIM;
wdenk9c53f402003-10-15 23:53:47 +0000200 lbc->br2 = CFG_BR2_PRELIM;
201 lbc->lbcr = CFG_LBC_LBCR;
wdenk492b9e72004-08-01 23:02:45 +0000202 asm("msync");
wdenk13eb2212004-07-09 23:27:13 +0000203
wdenk9c53f402003-10-15 23:53:47 +0000204 lbc->lsrt = CFG_LBC_LSRT;
wdenk9c53f402003-10-15 23:53:47 +0000205 lbc->mrtpr = CFG_LBC_MRTPR;
wdenk492b9e72004-08-01 23:02:45 +0000206 asm("sync");
wdenk9c53f402003-10-15 23:53:47 +0000207
wdenk13eb2212004-07-09 23:27:13 +0000208 /*
209 * Configure the SDRAM controller.
210 */
211 lbc->lsdmr = CFG_LBC_LSDMR_1;
wdenk492b9e72004-08-01 23:02:45 +0000212 asm("sync");
wdenk13eb2212004-07-09 23:27:13 +0000213 *sdram_addr = 0xff;
wdenk492b9e72004-08-01 23:02:45 +0000214 ppcDcbf((unsigned long) sdram_addr);
215 udelay(100);
wdenk9c53f402003-10-15 23:53:47 +0000216
wdenk13eb2212004-07-09 23:27:13 +0000217 lbc->lsdmr = CFG_LBC_LSDMR_2;
wdenk492b9e72004-08-01 23:02:45 +0000218 asm("sync");
wdenk13eb2212004-07-09 23:27:13 +0000219 *sdram_addr = 0xff;
wdenk492b9e72004-08-01 23:02:45 +0000220 ppcDcbf((unsigned long) sdram_addr);
221 udelay(100);
wdenk9c53f402003-10-15 23:53:47 +0000222
wdenk13eb2212004-07-09 23:27:13 +0000223 lbc->lsdmr = CFG_LBC_LSDMR_3;
wdenk492b9e72004-08-01 23:02:45 +0000224 asm("sync");
wdenk13eb2212004-07-09 23:27:13 +0000225 *sdram_addr = 0xff;
wdenk492b9e72004-08-01 23:02:45 +0000226 ppcDcbf((unsigned long) sdram_addr);
227 udelay(100);
wdenk9c53f402003-10-15 23:53:47 +0000228
wdenk13eb2212004-07-09 23:27:13 +0000229 lbc->lsdmr = CFG_LBC_LSDMR_4;
wdenk492b9e72004-08-01 23:02:45 +0000230 asm("sync");
wdenk13eb2212004-07-09 23:27:13 +0000231 *sdram_addr = 0xff;
wdenk492b9e72004-08-01 23:02:45 +0000232 ppcDcbf((unsigned long) sdram_addr);
233 udelay(100);
wdenk9c53f402003-10-15 23:53:47 +0000234
wdenk13eb2212004-07-09 23:27:13 +0000235 lbc->lsdmr = CFG_LBC_LSDMR_5;
wdenk492b9e72004-08-01 23:02:45 +0000236 asm("sync");
wdenk13eb2212004-07-09 23:27:13 +0000237 *sdram_addr = 0xff;
wdenk492b9e72004-08-01 23:02:45 +0000238 ppcDcbf((unsigned long) sdram_addr);
239 udelay(100);
wdenk9c53f402003-10-15 23:53:47 +0000240}
241
242
243#if defined(CFG_DRAM_TEST)
244int testdram (void)
245{
246 uint *pstart = (uint *) CFG_MEMTEST_START;
247 uint *pend = (uint *) CFG_MEMTEST_END;
248 uint *p;
249
250 printf("SDRAM test phase 1:\n");
251 for (p = pstart; p < pend; p++)
252 *p = 0xaaaaaaaa;
253
254 for (p = pstart; p < pend; p++) {
255 if (*p != 0xaaaaaaaa) {
256 printf ("SDRAM test fails at: %08x\n", (uint) p);
257 return 1;
258 }
259 }
260
261 printf("SDRAM test phase 2:\n");
262 for (p = pstart; p < pend; p++)
263 *p = 0x55555555;
264
265 for (p = pstart; p < pend; p++) {
266 if (*p != 0x55555555) {
267 printf ("SDRAM test fails at: %08x\n", (uint) p);
268 return 1;
269 }
270 }
271
272 printf("SDRAM test passed.\n");
273 return 0;
274}
275#endif
276
277
278#if !defined(CONFIG_SPD_EEPROM)
279/*************************************************************************
280 * fixed sdram init -- doesn't use serial presence detect.
281 ************************************************************************/
282long int fixed_sdram (void)
283{
284 #ifndef CFG_RAMBOOT
285 volatile immap_t *immap = (immap_t *)CFG_IMMR;
286 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
287
288 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
289 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
290 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
291 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
292 ddr->sdram_mode = CFG_DDR_MODE;
293 ddr->sdram_interval = CFG_DDR_INTERVAL;
294 #if defined (CONFIG_DDR_ECC)
295 ddr->err_disable = 0x0000000D;
296 ddr->err_sbe = 0x00ff0000;
297 #endif
298 asm("sync;isync;msync");
299 udelay(500);
300 #if defined (CONFIG_DDR_ECC)
301 /* Enable ECC checking */
302 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
303 #else
304 ddr->sdram_cfg = CFG_DDR_CONTROL;
305 #endif
306 asm("sync; isync; msync");
307 udelay(500);
308 #endif
wdenk13eb2212004-07-09 23:27:13 +0000309 return CFG_SDRAM_SIZE * 1024 * 1024;
wdenk9c53f402003-10-15 23:53:47 +0000310}
311#endif /* !defined(CONFIG_SPD_EEPROM) */
wdenk492b9e72004-08-01 23:02:45 +0000312
313
314#if defined(CONFIG_PCI)
315/*
316 * Initialize PCI Devices, report devices found.
317 */
318
wdenk492b9e72004-08-01 23:02:45 +0000319
Matthew McClintock8c0da862006-06-28 10:45:41 -0500320static struct pci_controller hose;
wdenk492b9e72004-08-01 23:02:45 +0000321
322#endif /* CONFIG_PCI */
323
324
325void
326pci_init_board(void)
327{
328#ifdef CONFIG_PCI
wdenk492b9e72004-08-01 23:02:45 +0000329 pci_mpc85xx_init(&hose);
330#endif /* CONFIG_PCI */
331}
Matthew McClintock148e26a2006-06-28 10:43:36 -0500332
333
334#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
335void
336ft_board_setup(void *blob, bd_t *bd)
337{
338 u32 *p;
339 int len;
340
Matthew McClintock8c0da862006-06-28 10:45:41 -0500341#ifdef CONFIG_PCI
342 ft_pci_setup(blob, bd);
343#endif
Matthew McClintock148e26a2006-06-28 10:43:36 -0500344 ft_cpu_setup(blob, bd);
345
346 p = ft_get_prop(blob, "/memory/reg", &len);
347 if (p != NULL) {
348 *p++ = cpu_to_be32(bd->bi_memstart);
349 *p = cpu_to_be32(bd->bi_memsize);
350 }
351}
352#endif