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git01.mediatek.com / filogic / uboot / b9d2a69e928da4c02f95de1c1b14a063bd90dd0f / . / include / configs / stm32f429-discovery.h
blob: 21bab5aafd5441e5c2ea895add1391e422ab42a7 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
rev13@wp.pl6b5e5a92015-03-01 12:44:42 +0100[diff] [blame]2/*
3 * (C) Copyright 2015
Kamil Lulko75d48a62015-12-01 09:08:19 +0100[diff] [blame]4 * Kamil Lulko, <kamil.lulko@gmail.com>
rev13@wp.pl6b5e5a92015-03-01 12:44:42 +0100[diff] [blame]5 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
rev13@wp.pl6b5e5a92015-03-01 12:44:42 +0100[diff] [blame]10#define CONFIG_SYS_FLASH_BASE 0x08000000
11
12#define CONFIG_SYS_INIT_SP_ADDR 0x10010000
rev13@wp.pl6b5e5a92015-03-01 12:44:42 +0100[diff] [blame]13
rev13@wp.pl6b5e5a92015-03-01 12:44:42 +0100[diff] [blame]14/*
15 * Configuration of the external SDRAM memory
16 */
rev13@wp.pl6b5e5a92015-03-01 12:44:42 +0100[diff] [blame]17
18#define CONFIG_SYS_MAX_FLASH_SECT 12
rev13@wp.pl6b5e5a92015-03-01 12:44:42 +0100[diff] [blame]19
rev13@wp.pl6b5e5a92015-03-01 12:44:42 +0100[diff] [blame]20#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
21
rev13@wp.pl6b5e5a92015-03-01 12:44:42 +0100[diff] [blame]22#define CONFIG_SYS_CBSIZE 1024
rev13@wp.pl6b5e5a92015-03-01 12:44:42 +0100[diff] [blame]23
rev13@wp.pl6b5e5a92015-03-01 12:44:42 +0100[diff] [blame]24#define CONFIG_EXTRA_ENV_SETTINGS \
25 "bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \
26 "bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \
27 "bootm 0x08044000 - 0x08042000\0"
28
rev13@wp.pl6b5e5a92015-03-01 12:44:42 +0100[diff] [blame]29#endif /* __CONFIG_H */